Harvard vs Von Neumann Architecture

In this article, we explain differences between the harvard and von neumann architecture, which are 2 most common architecture seen in microprocessors.

ARM processors, which are widely used in electronics uses harvard or von neumann architectures for its processors, with the latest designs moving more toward a harvard architecture.

So what is the difference really between these 2 architectures and which is more efficient?

We will see how harvard architecture holds several key advantages over von Neumann architecture, which is why the latest ARM processors use some form of a harvard architecture.

A harvard architecture is one in which the program instructions are stored and retrieved from a memory separate and distinct from the memory that holds data.

In von neumann architecture, instructions and data share a common memory.

Harvard architecture is superior in that concurrent instruction and data access can be carried out by the MCU during system processes due to the separate data and instruction memory units. This means that the MCU can retrieve data and instructions concurrently, meaning the process is faster and, thus, more efficient. This also means instructions can be fetched and executed in 4-byte chunks or 32 bits, while data can be simultaneously handled with 1-byte or 8-bit chunks. This is good because we are not using a one size fits all approach for instructions and data, and we can selectively target each with the necessary bits necessary.

With harvard architecture, instruction prefetches can be done in parallel with regular instruction executions, which speeds up the overall system performance.

Also, with harvard architecture, concurrent instruction and data access eliminates the need for data caches, which are typically used in von Neumann machines. This reduces system complexity and power consumption.

So, overall, harvard architecture's separate memory for data and instructions allow for a much faster concurrent parallel processing that defeats the serial approach of the von neumann architecture.

According to arm's website, developer.arm.com, memory protection units partition memory into regions. For each region, a user can specify the size, base address, and access permissions (such as read only access). When the protection unit is enabled, it aborts accesses to addresses outside any defined region.

ARM cached Harvard core have separate instruction and data caches, but use the same bus to access external memory.

The properties of memory regions for data and instructions can be defined separately.

Before the protection unit is enabled, at least one memory region for instructions and at least one memory region for data must be defined. These can define the same region of memory.

In von neumann architecture, von neumann cores access data and instructions over the same bus. One memory region must be defined before the protection unit is enabled.

This helps understand these differences directly from arm and this can be found at https://developer.arm.com/documentation/dui0056/d/caches-and-tightly-coupled-memories/memory-protection-units/harvard-architecture and https://developer.arm.com/documentation/dui0056/d/caches-and-tightly-coupled-memories/memory-protection-units/von-neumann-architecture

The Arm Cortext M0, M0+, and M1 all use the Von Neumann architecture, while the Arm Cortext M3, M4, M7, M33, M35P, M52, M55, and M85 all use the Harvard architecture. The Cortext M55, M85, and M52 are the 3 latest processors offered by ARM in 2020, 2022, and 2023, respectively, and they all use the harvard architecture.

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