How to Create a UART Receiver Interrupt Driver with an STM32F446 Microcontroller Board in C

In this article, we explain how to create a UART receiver interrupt driver with an STM32F446 microcontroller board in C.

UART stands for universal asynchronous receiver transmitter, and it is often used to transmit or receive data between a microcontroller and various components.

In our program, we will set it up so that we will allow for interrupts for our STM32 board to receive UART data from an outside device where both devices are set up for UART communication with one another.

When the secondary device sends information to our host device, the STM32 board, an interrupt is created and halts any program currently running (assuming the interrupt has a higher priority) and runs the UART interrupt service routine.

In this code, we are not actually going to code for priority, but this can be easily done. If you want, you can take a look at the article, How to Set the Priority of an External Interrupt with an STM32 board in C.

So previously, we created a program on, How to Receive Data with the UART Communication Protocol with an STM32F446 Board in C. If you need to, please familiarize yourself with how to receive data with the UART communication protocol first without interrupts, because we will not be going over all the code as extensively as this article. The explanations in this article are specifically more for just adding interrupts for UART communication to receive data.

So we take this program and modify it a bit by enabling the USART RXNEIE interrupt bit in the USART Control Register 1 and then enabling the interrupt for UART on the processor side, meaning for the Cortex-M4 processor.

We do both of these tasks within the the code to initialize the UART communication.

The next thing we need is an interrupt service routine for UART communication. This is the function our code will execute when an interrupt does occur. In this case, we will display the character pressed on a keyboard in the live expressions section of the STM32 software and if the character pressed is 'y', the green LED onboard will turn on. It's simply to demonstrate how we can run code through an interrupt service routine.

For this program, we will just be using the USART2_TX and USART2_RX pins, pins PA2 and PA3, respectively, for use of the UART communication. We don't actually have to do any connections at all.

The great thing about using the USART2 pins is that we can transmit or receive data using the UART protocol via USB.

So just connecting the STM32F446 board to your computer using a USB, you can allow for UART communication using a software. We will use the RealTerm software, which is a serial and TCP terminal for engineering and debugging.

We need 2 major code files in order for this code to work.

We need our header file, which contains many macros and structures that describe the various registers and needed values.

We then need our main C file, which contains the code that allows us to allow an interrupt to halt our program and execute the specific UART interrupt service routine.

Below is the header file that we will need for our code, which in this case is named, stm32f407xx.h


/* * stm32f446.h * * Created on: May 6, 2022 * Author: dlhyl */ #ifndef STM32F446_H_ #define STM32F446_H_ #include <stdint.h> #define __vo volatile #define IRQ_NO_EXTI0 6 #define IRQ_NO_EXTI1 7 #define IRQ_NO_EXTI2 8 #define IRQ_NO_EXTI3 9 #define IRQ_NO_EXTI4 10 #define IRQ_NO_EXTI9_5 23 #define IRQ_NO_EXTI15_10 40 //Processor specific details #define NVIC_ISER0 0xE000E100U #define NVIC_ISER1 0xE000E104U #define NVIC_ISER2 0xE000E108U #define NVIC_ISER3 0xE000E10CU volatile uint32_t* pNVIC_ISER0= ((volatile uint32_t*)NVIC_ISER0); volatile uint32_t* pNVIC_ISER1= ((volatile uint32_t*)NVIC_ISER1); volatile uint32_t* pNVIC_ISER2= ((volatile uint32_t*)NVIC_ISER2); volatile uint32_t* pNVIC_ISER3= ((volatile uint32_t*)NVIC_ISER3); #define NVIC_ICER0 0xE000E180U #define NVIC_ICER1 0xE000E184U #define NVIC_ICER2 0xE000E188U #define NVIC_ICER3 0xE000E18CU volatile uint32_t* pNVIC_ICERO= ((volatile uint32_t*)NVIC_ICER0); volatile uint32_t* pNVIC_ICER1= ((volatile uint32_t*)NVIC_ICER1); volatile uint32_t* pNVIC_ICER2= ((volatile uint32_t*)NVIC_ICER2); volatile uint32_t* pNVIC_ICER3= ((volatile uint32_t*)NVIC_ICER3); #define NVIC_PR_BASEADDR 0xE000E400U volatile uint32_t* pNVIC_PR_BASEADDR= ((volatile uint32_t*)NVIC_PR_BASEADDR); #define SYS_FREQ 16000000U #define APB1_CLK SYS_FREQ #define USART_BAUDRATE 115200 #define FLASH_BASEADDR 0x08000000U #define SRAM1_BASEADDR 0x20000000U #define SRAM2_BASEADDR 0x20001C00U #define ROM_BASEADDR 0x1FFF0000U #define SRAM SRAM1_BASEADDR #define PERIPH_BASEADDR 0x40000000U #define APB1PERIPH_BASEADDR PERIPH_BASEADDR #define APB2PERIPH_BASEADDR 0x40010000U #define AHB1PERIPH_BASEADDR 0x40020000U #define AHB2PERIPH_BASEADDR 0x50000000U //#define SYSCFG_BASEADDR 0x40013800U //#define EXTI_BASEADDR 0x40013C00U #define GPIOA_BASEADDR (AHB1PERIPH_BASEADDR + 0x0000) #define GPIOB_BASEADDR (AHB1PERIPH_BASEADDR + 0x0400) #define GPIOC_BASEADDR (AHB1PERIPH_BASEADDR + 0x0800) #define GPIOD_BASEADDR (AHB1PERIPH_BASEADDR + 0x0C00) #define GPIOE_BASEADDR (AHB1PERIPH_BASEADDR + 0x1000) #define GPIOF_BASEADDR (AHB1PERIPH_BASEADDR + 0x1400) #define GPIOG_BASEADDR (AHB1PERIPH_BASEADDR + 0x1800) #define GPIOH_BASEADDR (AHB1PERIPH_BASEADDR + 0x1C00) #define GPIOI_BASEADDR (AHB1PERIPH_BASEADDR + 0x2000) #define RCC_BASEADDR (AHB1PERIPH_BASEADDR + 0x3800) #define I2C1_BASEADDR (APB1PERIPH_BASEADDR + 0x5400) #define I2C2_BASEADDR (APB1PERIPH_BASEADDR + 0x5800) #define I2C3_BASEADDR (APB1PERIPH_BASEADDR + 0x5C00) #define SPI2_BASEADDR (APB1PERIPH_BASEADDR + 0x3800) #define SPI3_BASEADDR (APB1PERIPH_BASEADDR + 0x3C00) #define USART2_BASEADDR (APB1PERIPH_BASEADDR + 0x4400) #define USART3_BASEADDR (APB1PERIPH_BASEADDR + 0x4800) #define UART4_BASEADDR (APB1PERIPH_BASEADDR + 0x4C00) #define UART5_BASEADDR (APB1PERIPH_BASEADDR + 0x5000) #define EXTI_BASEADDR (APB2PERIPH_BASEADDR + 0x3C00) #define SPI1_BASEADDR (APB2PERIPH_BASEADDR + 0x3000) #define SPI4_BASEADDR (APB2PERIPH_BASEADDR + 0x3400) #define SYSCFG_BASEADDR (APB2PERIPH_BASEADDR + 0x3800) #define USART1_BASEADDR (APB2PERIPH_BASEADDR + 0x1000) #define USART6_BASEADDR (APB2PERIPH_BASEADDR + 0x1400) #define SPI5_BASEADDR (APB2PERIPH_BASEADDR + 0x5000) #define SPI6_BASEADDR (APB2PERIPH_BASEADDR + 0x5400) typedef struct { volatile uint32_t MODER; volatile uint32_t OTYPER; volatile uint32_t OSPEEDR; volatile uint32_t PUPDR; volatile uint32_t IDR; volatile uint32_t ODR; volatile uint32_t BSRR; volatile uint32_t LCKR; volatile uint32_t AFRL; volatile uint32_t AFRH; }GPIO_RegDef_t; #define GPIOA ((GPIO_RegDef_t*)GPIOA_BASEADDR) #define GPIOB ((GPIO_RegDef_t*)GPIOB_BASEADDR) #define GPIOC ((GPIO_RegDef_t*)GPIOC_BASEADDR) #define GPIOD ((GPIO_RegDef_t*)GPIOD_BASEADDR) #define GPIOE ((GPIO_RegDef_t*)GPIOE_BASEADDR) #define GPIOF ((GPIO_RegDef_t*)GPIOF_BASEADDR) #define GPIOG ((GPIO_RegDef_t*)GPIOG_BASEADDR) #define GPIOH ((GPIO_RegDef_t*)GPIOH_BASEADDR) #define GPIOI ((GPIO_RegDef_t*)GPIOI_BASEADDR) #define RCC ((RCC_RegDef_t*)RCC_BASEADDR) GPIO_RegDef_t *pGPIOA= GPIOA; GPIO_RegDef_t *pGPIOB= GPIOB; GPIO_RegDef_t *pGPIOC= GPIOC; GPIO_RegDef_t *pGPIOD= GPIOD; GPIO_RegDef_t *pGPIOE= GPIOE; GPIO_RegDef_t *pGPIOF= GPIOF; GPIO_RegDef_t *pGPIOG= GPIOG; GPIO_RegDef_t *pGPIOH= GPIOH; GPIO_RegDef_t *pGPIOI= GPIOI; typedef struct { volatile uint32_t CR; volatile uint32_t PLLCFGR; volatile uint32_t CFGR; volatile uint32_t CIR; volatile uint32_t AHB1RSTR; volatile uint32_t AHB2RSTR; volatile uint32_t AHB3RSTR; uint32_t RESERVED0; volatile uint32_t APB1RSTR; volatile uint32_t APB2RSTR; uint32_t RESERVED1[2]; volatile uint32_t AHB1ENR; volatile uint32_t AHB2ENR; volatile uint32_t AHB3ENR; uint32_t RESERVED2; volatile uint32_t APB1ENR; volatile uint32_t APB2ENR; uint32_t RESERVED3[2]; volatile uint32_t AHB1LPENR; volatile uint32_t AHB2LPENR; volatile uint32_t AHB3LPENR; uint32_t RESERVED4; volatile uint32_t APB1LPENR; volatile uint32_t APB2LPENR; uint32_t RESERVED5[2]; volatile uint32_t BDCR; volatile uint32_t CSR; uint32_t RESERVED6[2]; volatile uint32_t SSCGR; volatile uint32_t PLLI2SCFGR; volatile uint32_t PLLSAICFGR; volatile uint32_t DCKCFGR; volatile uint32_t CKGATENR; volatile uint32_t DCKCFGR2; }RCC_RegDef_t; RCC_RegDef_t *pRCC= RCC; typedef struct { volatile uint32_t MEMRMP; volatile uint32_t PMC; volatile uint32_t EXTICR1; volatile uint32_t EXTICR2; volatile uint32_t EXTICR3; volatile uint32_t EXTICR4; uint32_t RESERVED1[2]; volatile uint32_t CMPCR; }SYSCFG_RegDef_t; SYSCFG_RegDef_t *pSYSCFG= ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR); #define SYSCFG ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR) typedef struct { volatile uint32_t IMR; volatile uint32_t EMR; volatile uint32_t RTSR; volatile uint32_t FTSR; volatile uint32_t SWIER; volatile uint32_t PR; }EXTI_RegDef_t; EXTI_RegDef_t *pEXTI= ((EXTI_RegDef_t*)EXTI_BASEADDR); #define EXTI ((EXTI_RegDef_t*)EXTI_BASEADDR) typedef struct { volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t SR; volatile uint32_t DR; volatile uint32_t CRCPR; volatile uint32_t RXCRCR; volatile uint32_t TXCRCR; volatile uint32_t I2SCFGR; volatile uint32_t I2SPR; }SPI_RegDef_t; SPI_RegDef_t *pSPI1= ((SPI_RegDef_t*)SPI1_BASEADDR); SPI_RegDef_t *pSPI2= ((SPI_RegDef_t*)SPI2_BASEADDR); SPI_RegDef_t *pSPI3= ((SPI_RegDef_t*)SPI3_BASEADDR); SPI_RegDef_t *pSPI4= ((SPI_RegDef_t*)SPI4_BASEADDR); SPI_RegDef_t *pSPI5= ((SPI_RegDef_t*)SPI5_BASEADDR); SPI_RegDef_t *pSPI6= ((SPI_RegDef_t*)SPI6_BASEADDR); #define SPI1 ((SPI_RegDef_t*)SPI1_BASEADDR) #define SPI2 ((SPI_RegDef_t*)SPI2_BASEADDR) #define SPI3 ((SPI_RegDef_t*)SPI3_BASEADDR) #define SPI4 ((SPI_RegDef_t*)SPI4_BASEADDR) #define SPI5 ((SPI_RegDef_t*)SPI5_BASEADDR) #define SPI6 ((SPI_RegDef_t*)SPI6_BASEADDR) typedef struct { volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t OAR1; volatile uint32_t OAR2; volatile uint32_t DR; volatile uint32_t SR1; volatile uint32_t SR2; volatile uint32_t CCR; volatile uint32_t TRISE; volatile uint32_t FLTR; }I2C_RegDef_t; I2C_RegDef_t *pI2C1= ((I2C_RegDef_t*)I2C1_BASEADDR); I2C_RegDef_t *pI2C2= ((I2C_RegDef_t*)I2C2_BASEADDR); I2C_RegDef_t *pI2C3= ((I2C_RegDef_t*)I2C3_BASEADDR); #define I2C1 ((I2C_RegDef_t*)I2C1_BASEADDR) #define I2C2 ((I2C_RegDef_t*)I2C2_BASEADDR) #define I2C3 ((I2C_RegDef_t*)I2C3_BASEADDR) typedef struct { volatile uint32_t SR; volatile uint32_t DR; volatile uint32_t BRR; volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t CR3; volatile uint32_t GTPR; }USART_RegDef_t; USART_RegDef_t *pUSART1= ((USART_RegDef_t*)USART1_BASEADDR); USART_RegDef_t *pUSART2= ((USART_RegDef_t*)USART2_BASEADDR); USART_RegDef_t *pUSART3= ((USART_RegDef_t*)USART3_BASEADDR); USART_RegDef_t *pUART4= ((USART_RegDef_t*)UART4_BASEADDR); USART_RegDef_t *pUART5= ((USART_RegDef_t*)UART5_BASEADDR); USART_RegDef_t *pUSART6= ((USART_RegDef_t*)USART6_BASEADDR); #define USART1 ((USART_RegDef_t*)USART1_BASEADDR) #define USART2 ((USART_RegDef_t*)USART2_BASEADDR) #define USART3 ((USART_RegDef_t*)USART3_BASEADDR) #define USART4 ((USART_RegDef_t*)UART4_BASEADDR) #define USART5 ((USART_RegDef_t*)UART5_BASEADDR) #define USART6 ((USART_RegDef_t*)USART6_BASEADDR) #endif /* STM32F446_H_ */

So this header file contains all the definitions we need to create our main C file.

The contents of the main.c file is shown below.


#include <stdio.h> #include <stdint.h> #include "stm32f446.h" void usart2_txrx_interrupt_init(void); static uint16_t compute_usart_bd(uint32_t PCLK, uint32_t Baudrate); void USART2_IRQHandler(void); char key; int main(void) { //pRCC->AHB1ENR |= (1 << 0); usart2_txrx_interrupt_init(); while(1) { } } void usart2_txrx_interrupt_init(void) { //Turns on the clock for GPIO Port A pRCC->AHB1ENR |= (1 << 0); //Set PA5 as an output pin pGPIOA->MODER |= (0b01 << 10); //Sets PA2 to alternate function mode pGPIOA->MODER |= (0b10 << 4); //Sets pin PA2 to USART2_TX pGPIOA->AFRL |= (0b0111 << 8); //Sets PA3 to alternate function mode pGPIOA->MODER |= (0b10 << 6); //Sets pin PA3 to USART2_RX pGPIOA->AFRL |= (0b0111 << 12); //Turn on USART2 clock pRCC->APB1ENR |= (1 << 17); pUSART2->BRR |= compute_usart_bd(APB1_CLK, USART_BAUDRATE); //Enables transmitter and receiver pUSART2->CR1 = ((1 << 3) | (1 << 2)); //Enables USART RXNE interrupt pUSART2->CR1 |= (1 << 5); //Enable the interrupt for USART on the processor side *pNVIC_ISER1 |= (1 << 6); //Enables the USART pUSART2->CR1 |= (1 << 13); } static uint16_t compute_usart_bd(uint32_t PCLK, uint32_t Baudrate) { return ((PCLK + (Baudrate/2))/Baudrate); } void USART2_IRQHandler(void) { if(pUSART2->SR & (1 << 5)) { key= pUSART2->DR; if (key == 'y') { pGPIOA->ODR |= (1 << 5); } else{ pGPIOA->ODR &= ~(1 << 5); } } }

So we have to add the prototype for the interrupt service. We do this with the line, void USART2_IRQHandler(void);

Within our main() function, we initialize the uart communication.

You can then see that we have an empty infinite while loop.

This shows you that our code is run through interrupts and not through the main() function.

Within the initializing function, we turn on the clock for the GPIO Port A, set PA5 as otuput, set PA2 to function as USART2_TX, set PA3 to function as USART2_RX, turn on the clock for USART2, initialize the baud rate for the UART communication, enable the transmitter and receiver (though we could only do the receiver, since we are not doing any transmitting in this program).

We then enable the USART RXNEIE bit, which enables interrupts for receiving data in UART communication. This is done through the line, pUSART2->CR1 |= (1 << 5);

Below is the USART Control Register 1.

You can see that bit 5 is the RXNEIE bit, which allows for interrupts on the UART_RX connection for receiving data.

Next, we need to enable the interrupt for USART communication on the processor side, meaning the Cortex-M4 processor.

In order to do this, we need to gather information from both the microcontroller datasheet and the processor datasheet.

What we need from the microcontroller datasheet is to look at the datasheet for the position of the interrupt for USART2. If you do this for the STM32F446 microcontroller, you will see that this number is 38. So this is a very important number, because this is number will allow us to enable the USART2 interrupt.

Now we need to go to the processor datasheet for the Cortex-M4 processor.

There are a set of registers named the Interrupt Set-enable Registers (ISER), which allow us to enable interrupts.

This is shown below.

There are 8 of these registers in total, ISER0-ISER7.

Each register is 32 bits.

Each bit of a register controls a specific interrupt.

The reason that number 38 was so important for the USART2 interrupt is because that is bit in the ISER register that must be enabled to allow for USART2 interrupts.

We need to set HIGH bit 38 of the ISER register in order for USART2 interrupts to be enabled.

So in order to know which register and which bit to set high, we can use division to find the register and the modulus (%) to find the bit.

38/32 is 1, so we use the register ISER1.

38%32 is 6, so we set bit 6 of ISER1 HIGH to enable USART2 interrupts.

This is what we do in our code through the line, *pNVIC_ISER1 |= (1 << 6);

Lastly, we enable USART by setting bit 13 HIGH in the USART control register 1.

The next function is simply the function to compute the speed of communication of USART2.

Next we have our USART2 interrupt service routine handler.

So within this function, we use an if statement to check if any data has been sent and ready to be read. This we do with the USART status register, bit 5, which is the RXNE, which stands for, Read data register not empty.

We then copy the value to the data register.

If the key pressed is 'y', then the onboard LED connected to pin PA5 turns on. Else, if it is a different key, it turns off.

And this is how we can code a UART receiver interrupt driver with an STM32F446 board in C.

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