How to Create an I2C Driver with an STM32F446 Microcontroller Board in C

In this article, we explain how to create an I2C driver with an STM32F446 microcontroller board in C.

An I2C driver allows us to communicate with a device that uses the I2C communication protocol.

In our example, we will use our STM32 board as the master device and communicate with a slave device, a DS1307 real time clock. We will get information from this slave device to know its position.

The I2C, which stands for Inter-Integrated Circuit, communication protocol is a two-wire interface protocol that has 2 lines of transmission, SCL and SDA.

SCL is the serial clock line, which is used for synchronizing data transfer between the master and salve.

SDA is the serial data line, which is used to transfer the data.

The operation modes of the I2C protocol is either Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver.

With the I2C protocol, transactions are initiated and completed by the master device.

All messages have an address frame and a data frame.

Data is placed on the SDA line after SCL goes LOW, and it is sampled after the SCL line goes HIGH.

In our sample program, we will use an STM32 board with a DS1307 real time clock.

Because the DS1307 real time clock, as pretty much all components need, require power, we need to connect the component to +5V and GND, in order to power it.

Because we are using the I2C communication protocol, which is a two-wire protocol, we need to make 2 connections, SCL and SDA, to establish I2C communication between the STM32 board and the DS1307 real time clock.

So, in total, 4 wire connections are needed between the STM32 board and the real time clock.

The circuit schematic for the circuit we will build is shown below.

So, after this hardware connection is made, the only thing we need now is the software to execute on the board.

We should then be able to read the time that the real time clock gives us.

So below is the code needed in order to run this real time clock circuit.

Before we go directly into our main C code, there are some supporting files we need, including register maps and macros needed.

Below we have the stm32f446.h file, which contains many register maps (including for the I2C register) and macros needed for the software program.


/* * stm32f446.h * * Created on: May 6, 2022 * Author: dlhyl */ #ifndef STM32F446_H_ #define STM32F446_H_ #include <stdint.h> #define __vo volatile #define IRQ_NO_EXTI0 6 #define IRQ_NO_EXTI1 7 #define IRQ_NO_EXTI2 8 #define IRQ_NO_EXTI3 9 #define IRQ_NO_EXTI4 10 #define IRQ_NO_EXTI9_5 23 #define IRQ_NO_EXTI15_10 40 //Processor specific details #define NVIC_ISER0 0xE000E100U #define NVIC_ISER1 0xE000E104U #define NVIC_ISER2 0xE000E108U #define NVIC_ISER3 0xE000E10CU volatile uint32_t* pNVIC_ISER0= ((volatile uint32_t*)NVIC_ISER0); volatile uint32_t* pNVIC_ISER1= ((volatile uint32_t*)NVIC_ISER1); volatile uint32_t* pNVIC_ISER2= ((volatile uint32_t*)NVIC_ISER2); volatile uint32_t* pNVIC_ISER3= ((volatile uint32_t*)NVIC_ISER3); #define NVIC_ICER0 0xE000E180U #define NVIC_ICER1 0xE000E184U #define NVIC_ICER2 0xE000E188U #define NVIC_ICER3 0xE000E18CU volatile uint32_t* pNVIC_ICERO= ((volatile uint32_t*)NVIC_ICER0); volatile uint32_t* pNVIC_ICER1= ((volatile uint32_t*)NVIC_ICER1); volatile uint32_t* pNVIC_ICER2= ((volatile uint32_t*)NVIC_ICER2); volatile uint32_t* pNVIC_ICER3= ((volatile uint32_t*)NVIC_ICER3); #define NVIC_PR_BASEADDR 0xE000E400U volatile uint32_t* pNVIC_PR_BASEADDR= ((volatile uint32_t*)NVIC_PR_BASEADDR); #define SYS_FREQ 16000000U #define APB1_CLK SYS_FREQ #define USART_BAUDRATE 115200 #define FLASH_BASEADDR 0x08000000U #define SRAM1_BASEADDR 0x20000000U #define SRAM2_BASEADDR 0x20001C00U #define ROM_BASEADDR 0x1FFF0000U #define SRAM SRAM1_BASEADDR #define PERIPH_BASEADDR 0x40000000U #define APB1PERIPH_BASEADDR PERIPH_BASEADDR #define APB2PERIPH_BASEADDR 0x40010000U #define AHB1PERIPH_BASEADDR 0x40020000U #define AHB2PERIPH_BASEADDR 0x50000000U //#define SYSCFG_BASEADDR 0x40013800U //#define EXTI_BASEADDR 0x40013C00U #define GPIOA_BASEADDR (AHB1PERIPH_BASEADDR + 0x0000) #define GPIOB_BASEADDR (AHB1PERIPH_BASEADDR + 0x0400) #define GPIOC_BASEADDR (AHB1PERIPH_BASEADDR + 0x0800) #define GPIOD_BASEADDR (AHB1PERIPH_BASEADDR + 0x0C00) #define GPIOE_BASEADDR (AHB1PERIPH_BASEADDR + 0x1000) #define GPIOF_BASEADDR (AHB1PERIPH_BASEADDR + 0x1400) #define GPIOG_BASEADDR (AHB1PERIPH_BASEADDR + 0x1800) #define GPIOH_BASEADDR (AHB1PERIPH_BASEADDR + 0x1C00) #define GPIOI_BASEADDR (AHB1PERIPH_BASEADDR + 0x2000) #define RCC_BASEADDR (AHB1PERIPH_BASEADDR + 0x3800) #define DMA1_BASEADDR (AHB1PERIPH_BASEADDR + 0x6000) #define DMA2_BASEADDR (AHB1PERIPH_BASEADDR + 0x6400) #define I2C1_BASEADDR (APB1PERIPH_BASEADDR + 0x5400) #define I2C2_BASEADDR (APB1PERIPH_BASEADDR + 0x5800) #define I2C3_BASEADDR (APB1PERIPH_BASEADDR + 0x5C00) #define SPI2_BASEADDR (APB1PERIPH_BASEADDR + 0x3800) #define SPI3_BASEADDR (APB1PERIPH_BASEADDR + 0x3C00) #define USART2_BASEADDR (APB1PERIPH_BASEADDR + 0x4400) #define USART3_BASEADDR (APB1PERIPH_BASEADDR + 0x4800) #define UART4_BASEADDR (APB1PERIPH_BASEADDR + 0x4C00) #define UART5_BASEADDR (APB1PERIPH_BASEADDR + 0x5000) #define EXTI_BASEADDR (APB2PERIPH_BASEADDR + 0x3C00) #define SPI1_BASEADDR (APB2PERIPH_BASEADDR + 0x3000) #define SPI4_BASEADDR (APB2PERIPH_BASEADDR + 0x3400) #define SYSCFG_BASEADDR (APB2PERIPH_BASEADDR + 0x3800) #define USART1_BASEADDR (APB2PERIPH_BASEADDR + 0x1000) #define USART6_BASEADDR (APB2PERIPH_BASEADDR + 0x1400) #define SPI5_BASEADDR (APB2PERIPH_BASEADDR + 0x5000) #define SPI6_BASEADDR (APB2PERIPH_BASEADDR + 0x5400) typedef struct { volatile uint32_t MODER; volatile uint32_t OTYPER; volatile uint32_t OSPEEDR; volatile uint32_t PUPDR; volatile uint32_t IDR; volatile uint32_t ODR; volatile uint32_t BSRR; volatile uint32_t LCKR; volatile uint32_t AFRL; volatile uint32_t AFRH; }GPIO_RegDef_t; #define GPIOA ((GPIO_RegDef_t*)GPIOA_BASEADDR) #define GPIOB ((GPIO_RegDef_t*)GPIOB_BASEADDR) #define GPIOC ((GPIO_RegDef_t*)GPIOC_BASEADDR) #define GPIOD ((GPIO_RegDef_t*)GPIOD_BASEADDR) #define GPIOE ((GPIO_RegDef_t*)GPIOE_BASEADDR) #define GPIOF ((GPIO_RegDef_t*)GPIOF_BASEADDR) #define GPIOG ((GPIO_RegDef_t*)GPIOG_BASEADDR) #define GPIOH ((GPIO_RegDef_t*)GPIOH_BASEADDR) #define GPIOI ((GPIO_RegDef_t*)GPIOI_BASEADDR) #define RCC ((RCC_RegDef_t*)RCC_BASEADDR) GPIO_RegDef_t *pGPIOA= GPIOA; GPIO_RegDef_t *pGPIOB= GPIOB; GPIO_RegDef_t *pGPIOC= GPIOC; GPIO_RegDef_t *pGPIOD= GPIOD; GPIO_RegDef_t *pGPIOE= GPIOE; GPIO_RegDef_t *pGPIOF= GPIOF; GPIO_RegDef_t *pGPIOG= GPIOG; GPIO_RegDef_t *pGPIOH= GPIOH; GPIO_RegDef_t *pGPIOI= GPIOI; typedef struct { volatile uint32_t CR; volatile uint32_t PLLCFGR; volatile uint32_t CFGR; volatile uint32_t CIR; volatile uint32_t AHB1RSTR; volatile uint32_t AHB2RSTR; volatile uint32_t AHB3RSTR; uint32_t RESERVED0; volatile uint32_t APB1RSTR; volatile uint32_t APB2RSTR; uint32_t RESERVED1[2]; volatile uint32_t AHB1ENR; volatile uint32_t AHB2ENR; volatile uint32_t AHB3ENR; uint32_t RESERVED2; volatile uint32_t APB1ENR; volatile uint32_t APB2ENR; uint32_t RESERVED3[2]; volatile uint32_t AHB1LPENR; volatile uint32_t AHB2LPENR; volatile uint32_t AHB3LPENR; uint32_t RESERVED4; volatile uint32_t APB1LPENR; volatile uint32_t APB2LPENR; uint32_t RESERVED5[2]; volatile uint32_t BDCR; volatile uint32_t CSR; uint32_t RESERVED6[2]; volatile uint32_t SSCGR; volatile uint32_t PLLI2SCFGR; volatile uint32_t PLLSAICFGR; volatile uint32_t DCKCFGR; volatile uint32_t CKGATENR; volatile uint32_t DCKCFGR2; }RCC_RegDef_t; RCC_RegDef_t *pRCC= RCC; typedef struct { volatile uint32_t MEMRMP; volatile uint32_t PMC; volatile uint32_t EXTICR1; volatile uint32_t EXTICR2; volatile uint32_t EXTICR3; volatile uint32_t EXTICR4; uint32_t RESERVED1[2]; volatile uint32_t CMPCR; }SYSCFG_RegDef_t; SYSCFG_RegDef_t *pSYSCFG= ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR); #define SYSCFG ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR) typedef struct { volatile uint32_t IMR; volatile uint32_t EMR; volatile uint32_t RTSR; volatile uint32_t FTSR; volatile uint32_t SWIER; volatile uint32_t PR; }EXTI_RegDef_t; EXTI_RegDef_t *pEXTI= ((EXTI_RegDef_t*)EXTI_BASEADDR); #define EXTI ((EXTI_RegDef_t*)EXTI_BASEADDR) typedef struct { volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t SR; volatile uint32_t DR; volatile uint32_t CRCPR; volatile uint32_t RXCRCR; volatile uint32_t TXCRCR; volatile uint32_t I2SCFGR; volatile uint32_t I2SPR; }SPI_RegDef_t; SPI_RegDef_t *pSPI1= ((SPI_RegDef_t*)SPI1_BASEADDR); SPI_RegDef_t *pSPI2= ((SPI_RegDef_t*)SPI2_BASEADDR); SPI_RegDef_t *pSPI3= ((SPI_RegDef_t*)SPI3_BASEADDR); SPI_RegDef_t *pSPI4= ((SPI_RegDef_t*)SPI4_BASEADDR); SPI_RegDef_t *pSPI5= ((SPI_RegDef_t*)SPI5_BASEADDR); SPI_RegDef_t *pSPI6= ((SPI_RegDef_t*)SPI6_BASEADDR); #define SPI1 ((SPI_RegDef_t*)SPI1_BASEADDR) #define SPI2 ((SPI_RegDef_t*)SPI2_BASEADDR) #define SPI3 ((SPI_RegDef_t*)SPI3_BASEADDR) #define SPI4 ((SPI_RegDef_t*)SPI4_BASEADDR) #define SPI5 ((SPI_RegDef_t*)SPI5_BASEADDR) #define SPI6 ((SPI_RegDef_t*)SPI6_BASEADDR) typedef struct { volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t OAR1; volatile uint32_t OAR2; volatile uint32_t DR; volatile uint32_t SR1; volatile uint32_t SR2; volatile uint32_t CCR; volatile uint32_t TRISE; volatile uint32_t FLTR; }I2C_RegDef_t; I2C_RegDef_t *pI2C1= ((I2C_RegDef_t*)I2C1_BASEADDR); I2C_RegDef_t *pI2C2= ((I2C_RegDef_t*)I2C2_BASEADDR); I2C_RegDef_t *pI2C3= ((I2C_RegDef_t*)I2C3_BASEADDR); #define I2C1 ((I2C_RegDef_t*)I2C1_BASEADDR) #define I2C2 ((I2C_RegDef_t*)I2C2_BASEADDR) #define I2C3 ((I2C_RegDef_t*)I2C3_BASEADDR) typedef struct { volatile uint32_t SR; volatile uint32_t DR; volatile uint32_t BRR; volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t CR3; volatile uint32_t GTPR; }USART_RegDef_t; USART_RegDef_t *pUSART1= ((USART_RegDef_t*)USART1_BASEADDR); USART_RegDef_t *pUSART2= ((USART_RegDef_t*)USART2_BASEADDR); USART_RegDef_t *pUSART3= ((USART_RegDef_t*)USART3_BASEADDR); USART_RegDef_t *pUART4= ((USART_RegDef_t*)UART4_BASEADDR); USART_RegDef_t *pUART5= ((USART_RegDef_t*)UART5_BASEADDR); USART_RegDef_t *pUSART6= ((USART_RegDef_t*)USART6_BASEADDR); #define USART1 ((USART_RegDef_t*)USART1_BASEADDR) #define USART2 ((USART_RegDef_t*)USART2_BASEADDR) #define USART3 ((USART_RegDef_t*)USART3_BASEADDR) #define USART4 ((USART_RegDef_t*)UART4_BASEADDR) #define USART5 ((USART_RegDef_t*)UART5_BASEADDR) #define USART6 ((USART_RegDef_t*)USART6_BASEADDR) //DMA typedef struct { volatile uint32_t LISR; //0x000 volatile uint32_t HISR; //0x004 volatile uint32_t LIFCR; //0x008 volatile uint32_t HIFCR; //0x00C volatile uint32_t S0CR; //0x010 volatile uint32_t S0NDTR; //0x014 volatile uint32_t S0PAR; //0x018 volatile uint32_t S0M0AR; //0x01C volatile uint32_t S0M1AR; //0x020 volatile uint32_t S0FCR; //0x024 volatile uint32_t S1CR; //0x028 volatile uint32_t S1NDTR; //0x02C volatile uint32_t S1PAR; //0x030 volatile uint32_t S1M0AR; //0x034 volatile uint32_t S1M1AR; //0x038 volatile uint32_t S1FCR; //0x03C volatile uint32_t S2CR; //0x040 volatile uint32_t S2NDTR; //0x044 volatile uint32_t S2PAR; //0x048 volatile uint32_t S2M0AR; //0x04C volatile uint32_t S2M1AR; //0x050 volatile uint32_t S2FCR; //0x054 volatile uint32_t S3CR; //0x058 volatile uint32_t S3NDTR; //0x05C volatile uint32_t S3PAR; //0x060 volatile uint32_t S3M0AR; //0x064 volatile uint32_t S3M1AR; //0x068 volatile uint32_t S3FCR; //0x06C volatile uint32_t S4CR; //0x070 volatile uint32_t S4NDTR; //0x074 volatile uint32_t S4PAR; //0x078 volatile uint32_t S4M0AR; //0x07C volatile uint32_t S4M1AR; //0x080 volatile uint32_t S4FCR; //0x084 volatile uint32_t S5CR; //0x088 volatile uint32_t S5NDTR; //0x08C volatile uint32_t S5PAR; //0x090 volatile uint32_t S5M0AR; //0x094 volatile uint32_t S5M1AR; //0x098 volatile uint32_t S5FCR; //0x09C volatile uint32_t S6CR; //0x0A0 volatile uint32_t S6NDTR; //0x0A4 volatile uint32_t S6PAR; //0x0A8 volatile uint32_t S6M0AR; //0x0AC volatile uint32_t S6M1AR; //0x0B0 volatile uint32_t S6FCR; //0x0B4 volatile uint32_t S7CR; //0x0B8 volatile uint32_t S7NDTR; //0x0BC volatile uint32_t S7PAR; //0x0C0 volatile uint32_t S7M0AR; //0x0C4 volatile uint32_t S7M1AR; //0x0C8 volatile uint32_t S7FCR; //0x0CC }DMA_RegDef_t; DMA_RegDef_t *pDMA1= ((DMA_RegDef_t*)DMA1_BASEADDR); DMA_RegDef_t *pDMA2= ((DMA_RegDef_t*)DMA2_BASEADDR); #define DMA1 ((DMA_RegDef_t*)DMA1_BASEADDR) #define DMA2 ((DMA_RegDef_t*)DMA2_BASEADDR) #endif /* STM32F446_H_ */

So we can now go to our main.c file.


#include <stdio.h> #include <stdint.h> #include "stm32f446.h" #include "ds1307.h" void I2C1_init(void); void I2C1_byteRead(char slaveaddress, char memoryaddress, char* data); void delayMs(int n); #define SLAVE_ADDR 0x68 int main(void) { I2C1_init(); pRCC->AHB1ENR |= (1 << 0); pGPIOA->MODER |= (0b01 << 5); char data; while(1) { I2C1_byteRead(SLAVE_ADDR, 0, &data); if(data & 1) { pGPIOA->ODR |= (1 << 5); } else { pGPIOA->ODR &= ~(1 << 5); delayMs(10); } } } void I2C1_init(void) { //Enable clock access to GPIOB pRCC->AHB1ENR |= (1 << 1); //Configure pin PB8 in alternate function mode //to be I2C1_SCL (AF4) pGPIOB->MODER |= (0b10 << 16); pGPIOB->AFRH |= (0b0100 << 0); //Configure pin PB9 in alternate function mode //to be I2C1_SDA (AF4) pGPIOB->MODER |= (0b10 << 18); pGPIOB->AFRH |= (0b0100 << 4); //Set PB8 and PB9 output type to open drain pGPIOB->OTYPER |= (1 << 8); pGPIOB->OTYPER |= (1 << 9); //Enable pull-up resistors for PB8 and PB9 pGPIOB->PUPDR |= (0b01 << 16); pGPIOB->PUPDR |= (0b01 << 18); //Enable clock access to I2C1 pRCC->APB1ENR |= (1 << 21); //Set I2C1 to be under reset state pI2C1->CR1 |= (1 << 15); //Come out of reset state pI2C1->CR1 &= ~(1 << 15); //Set clock frequency of I2C1 to be 16MHz //pI2C1->CR2 = (0b010000 << 0); pI2C1->CR2 = (1U << 4); //Set I2C clock to standard mode- 100KHz //pI2C1->CCR = (0b01010000 << 0); pI2C1->CCR = 80; //Sets rise time pI2C1->TRISE = 17; //Enable I2C1 pI2C1->CR1 |= (1 << 0); } void I2C1_byteRead(char slaveaddress, char memoryaddress, char* data) { volatile int tmp; //Wait until I2C1 is no longer busy while((pI2C1->SR2) & (1U << 1)); //Generate start pI2C1->CR1 |= (1 << 8); //Wait until start flag is set while(!((pI2C1->SR1) & (1U << 0))); //Transmit slave address + Write pI2C1->DR = slaveaddress << 1; //Wait until addr flag is set while(!((pI2C1->SR1) & (1U << 1))); //Clear addr flag tmp= pI2C1->SR2; //tentative while(!((pI2C1->SR1) & (1U << 7))); //Send memory address pI2C1->DR = memoryaddress; //Wait until transmitter is empty while(!((pI2C1->SR1) & (1U << 7))); //Generate restart condition pI2C1->CR1 |= (1 << 8); //Wait until start flag is set while(!(pI2C1->SR1 & (1 << 0))); //Transmit slave address + Read pI2C1->DR = slaveaddress << 1 | 1; //Wait until addr flag is set while(!(pI2C1->SR1 & (1U << 1))); //Disable Acknowledge (ACK) pI2C1->CR1 &= ~(1 << 10); //Clear addr flag tmp= pI2C1->SR2; //Generate stop pI2C1->CR1 |= (1 << 9); //Wait until RXNE flag is set while(!(pI2C1->SR1 & (1U << 6))); //Read data from DR *data++ = pI2C1->DR; } void delayMs(int n){ for(;n>0; n--){ for(int i=0; i<3195; i++); } }

So this code is somewhat long, so we will break it down to make it understandable.

So we first include the header files we need.

We then have a list of the function prototypes, so that the compiler knows about them, as in what they return and what parameters they take in, as well as the parameter types.

We then define a number of variables, which we use in our program. We will get back to these, as well as the main() function.

Instead now we skip ahead to the I2C1_init() function, which initializes the I2C communication protocol so that we can use it to communicate with the ADXL345 accelerometer device.

So we can start taking a look at charts.

Below is the alternate function mapping of GPIO Port B for an STM32F446 microcontroller board.

So you can see that in AF4, pin PB8 functions as I2C1_SCL and pin PB9 function as I2C1_SDA.

This is important to know because these are the 2 pins that we use for I2C communication.

I2C has 3 channels in an STM32F446 board, I2C1, I2C2, and I2C3. I2C1 is the one we are using in this case.

So because we are using GPIO Port B, we must enable the clock for GPIOB.

After this, we must enable the clock to I2C1. I2C1 (as well as I2C2 and I2C3) are all connected to the APB1 bus.

To turn on the clock for I2C1, we write a 1 to bit 21 of the APB1ENR register.

We then must configure pin PB8 to be in alternate function mode. This we do by writing 0b10 to bit 16 to the GPIOx_MODER register.

We then go to the AFHR (Alternate Function High Register) and we write 0b0100 to bit 0 in order to put pin PB8 in AF4, which makes it act as I2C1_SCL.

We then do the same for pin PB9, putting the pin in alternate function mode with the MODER register and then setting the mode to AF4 with the AFHR register.

An important thing to remember with the I2C communication protocol is that the various pins must be in open drain configuration. I2C does not operate with push-pull mode. Therefore, we must set this for pins PB8 and PB9 in the OTYPER register.

Another important thing for the I2C communication protocol is having pull-up resistors for each of the pins, SCL and SDA. You don't have to physically connect these lines to pull-up resistors. It is sufficient to connect these pins to pull-up resistors in software. We do this in our code with the PUPDR register.

Next, we begin setting bits of the I2C registers to configure I2C settings.

Below is the I2C control register 1.

First, we must reset I2C1 and then come out of the reset state. This is done by setting bit 15 to 1 and then clearing it and setting it back to its default state of 0.

We then must set the clock frequency of I2C1 to 16MHz. We do this in the control register 2.

This register is shown below.

Bits 5:0 are the bits that set the peripheral clock frequency. Since we want to set the frequency to 16MHz, we have to write out the binary equivalent of 16 to these bits, which is 010000. Therefore, we feed 0b010000 into these bits to get a clock frequency of 16MHz. Each bit signifies the frequency in MHz. So if we set this bit to a value of 2, this would be a frequency of 2MHz. According to the datasheet, the minimum allowed frequency is 2 MHz and the maximum frequency is limited by the maximum APB frequency (45 MHz) and cannot exceed 50 MHz (peripheral intrinsic maximum limit).

To set the I2C clock to standard mode (100KHz), we feed the value of 0b01010000 into the I2C clock control register (I2C_CCR).

We then must set the rise time of the clock signal, which is how long it takes for a clock to go from a LOW logic state to a HIGH logic state. According to the datasheet, in standard mode, the maximum allowed SCL rise time is 1000 ns. We simply set our value to 17.

Lastly, we can then enable the I2C1. We do this by setting bit 0, the peripheral enable bit, to 1. This turns on the I2C communication protocol.

So we then have our next function, I2C1_byteRead().

This function takes in 3 parameters: slaveadress, memoryaddress, and data.

We create a volatile integer variable named tmp.

The first thing we must do is wait until I2C1 is no longer busy.

We can check this with the Busy bit, bit 1, on the I2C status register 2.

This register is shown below.

As long as the bit is 1, there is ongoing communication on the bus. We must wait until this bit is cleared to 0 before we continue on with our program.

Once the bus is not busy, we generate a start condition. This is done by setting the start bit, bit 8, of the control register 1 to HIGH.

Then we must wait until the start flag is set.

We then attempt to communicate with the slave device. WE do this by transmitting the address of the slave device and then we must specify whether we are looking to write to the slave device or read from the slave device. When we are looking to make contact with a slave device, it is always a write.

When we are attempting to communicate with a slave device, we write the address to the data register.

The data register is shown below.

Notice how this register only takes a byte of data (8 bits). Slave addresses can never be longer than 8 bits in order for the master to be able to identify the slave it wants to communicate with.

So after we write this slave address to the data register, we must then wait until the address flag in the status register 1 to be set.

The I2C status register 1 is shown below.

This address bit is very important, as this signals that the master has successfully communicated with the slave device. If the

If the address bit sets and is then cleared, then successful communication has been made from the master to the slave device.

The 2 devices can then do more commmunicating later.

If the address bit does not set, this signifies that the master was not able to successfully communicate with the slave device. This could be because the address is incorrect or there is some incorrect hardware setup such as no pull-up resistors to VCC or incorrect resistor values. It's best to use resistors between 2KΩ-4KΩ. The internal pull-up resistors used in software are around 40K, which is too high for I2C communication. So there are a variety of different reasons why the address bit wouldn't set, so troubleshooting is required.

We then clear the address flag by the line, tmp= pI2C1->SR2;

So the slave address is the fixed address created by the manufacturer, so that a master device can identify it. You can see it as the external address of the slave device.

The memory address is the address of the register we want to read from or write to in the slave device.

We send the memory address (which is the data register of the slave device) we wish to read from or write to by writing this memory address by sending this address to the data register, just like we did with the slave address.

We then must wait until the transmitter is empty, which we can check by checking the TxE bit, bit 7, of status register 1. If the value of the TxE register is 1, then the data register is not empty, which means transmission is still in progress. We must wait for the bit value to be 0, which means the data register is empty which means transmission is complete.

We must then generate a restart condition and wait until the start flag is set, as we did previously.

We then transmit the slave address this time with read. We then wait until the address flag is set.

We then disable the acknowledge bit.

We then clear the address flag.

We then generate a stop condition.

We then wait until the RXNE flag to be cleared, meaning the data register is empty.

We then read the data from the data register.

We then have a delay function.

Now we go back to our main() function.

So we run the I2C1_init() function in order to initialize the I2C1 communication.

We then turn on the clock for GPIO Port A, because we are going to turn on the LED at PA5. We set pin PA5 as output.

We then have our infinite while loop.

In this while loop, we have simple code.

We use the I2C1_byteRead() in this infinite loop, because we are always going to continouously be reading from this register.

The I2C1_byteRead() function takes in 3 parameters.

The first parameter is the slave address, so that the master (the STM32 board) can identify that the slave device (the DS1307 real time clock).

The second parameter is the memory address, which in this case is 0. What 0 represents is the second data of the real time clock.

The third parameter is the data itself.

This program has the effect of creating a blinking LED.

And this is how a very basic program of how I2C communication works with an STM32 board and a slave device that uses the I2C protocol.

This I2C driver program serves as an example that can be applied to any I2C slave device, such as an accelerometer, humidity sensor, or any other type of I2C device.

And this is how to create an I2C driver with an STM32F446 microcontroller board in C.

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