How to Enable a GPIO Pin to Function as the Source of an External Interrupt with an STM32F407G Microcontroller Board in C

In this article, we explain how to enable a GPIO pin to function as the source of an external interrupt with an STM32F407G microcontroller board in C.

With the GPIO port pin in this configuration, we can cause any various event on this pin to trigger an interrupt service routine (ISR), which exits the program and runs this interrupt function.

In this project specifically, we configure GPIO port A pin 0 to function as the source of an external interrupt. We connect a push button to this pin. We connect the push button to a pull up resistor to VDD. When the push button is pressed, this HIGH voltage state transitions to a LOW voltage state. With the interrupt being triggered with a falling edge signal, the interrupt gets triggered. We then connect an LED to GPIO port A pin 1, which will toggle the LED with each button press.

This project serves to teach you how external interrupts work and specifically how to configure GPIO pins to function as sources of external interrupts.

External interrupts can appear as well from other pins, not just general-purpose GPIO pins.

External interrupts can be triggered from GPIO pins in alternate function mode such as SPI, I2C, UART, USB, etc.

In this article, we specifically deal with configuring GPIO pins to function as sources of external interrupts.

So let's now talk about how this works.

So STM32 boards come with multiple GPIO pins that have 16 pins each. This is the case with the STM32F407G board.

Any of the 16 pins of any GPIO port can function as the source of an external interrupt.

Below is a diagram that helps to illustrate how this process works.

We will explain it in detail below.

So to the leftmost of the diagram, you see the GPIO pins.

Next, you see a module named EXTI, which stands for the External interrupt/event controller.

This controller can select whether the input is an interrupt or event, and whether the event is triggered by a rising edge, a falling edge, or both.

This controller also has an interrupt mask register, which allows for the enabling or disabling of the interrupt delivery to the processor.

You then see that there is a module labeled NVIC. The NVIC stands for nested vector interrupt controller, and it is present within the actual processor (the Cortex-M processor) of the microcontroller. This is because interrupts are ultimately handled by the processor. They originate from peripheral components such as the GPIO pins on the microcontroller board (outside of the processor) but they have to be processed by the NVIC register in the core processor of the board.

You can see numbers on the NVIC register. These are referred to as IRQ (interrupt request) values.

We must enable the appropriate IRQ for the corresponding GPIO pin we are sourcing the external interrupt from.

For GPIO pin 0, this is IRQ number 6.

For GPIO pin 1, this is IRQ number 7.

For GPIO pin 2, this is IRQ number 8.

For GPIO pin 3, this is IRQ number 9.

For GPIO pin 4, this is IRQ number 10.

For GPIO pins 5 to 9, this is IRQ number 23.

For GPIO pins 10 to 15, this is IRQ number 40.

Pins 5 to 9 are grouped together, as well as pins 10-15. This is because they all use the same IRQ number.

Once we enable the IRQ number via the Interrupt Set-enable register of the Cortex-M processor, the processor will process the interrupt from the peripheral component on that line.

Once an interrupt is performed on that line, a pending register will be set, which will then jump to the ISR function for that interrupt line, and the action that we coded will be performed for that interrupt request.

So that is basically how external interrupts work for GPIO pins with STM32 boards.

Again, we will be using GPIO port A pin 0 as the source of an external interrupt. We will connect a push button to this pin which is pulled up to VDD via an internal pull-up resistor. We then configure the interrupt to be triggered during a falling edge. This will then cause the ISR to be executed and our function to be executed.

The circuit we will build is shown in the diagram below.

We need 2 major code files in order for this code to work.

We need our header file, which contains many macros and structures that describe the various registers and needed values.

We then need our main C file, which contains the code to execute the ISR when an external interrupt is triggered (by pushing down the push button).

Below is the header file that we will need for our code, which in this case is named, stm32f407xx.h


/* * stm32f407xx.h * * Created on: Apr 26, 2022 * Author: dlhyl */ #ifndef INC_STM32F407XX_H_ #define INC_STM32F407XX_H_ #include <stdint.h> #define __vo volatile #define IRQ_NO_EXTI0 6 #define IRQ_NO_EXTI1 7 #define IRQ_NO_EXTI2 8 #define IRQ_NO_EXTI3 9 #define IRQ_NO_EXTI4 10 #define IRQ_NO_EXTI9_5 23 #define IRQ_NO_EXTI15_10 40 //Processor specific details #define NVIC_ISER0 0xE000E100U #define NVIC_ISER1 0xE000E104U #define NVIC_ISER2 0xE000E108U #define NVIC_ISER3 0xE000E10CU volatile uint32_t* pNVIC_ISERO= ((volatile uint32_t*)NVIC_ISER0); volatile uint32_t* pNVIC_ISER1= ((volatile uint32_t*)NVIC_ISER1); volatile uint32_t* pNVIC_ISER2= ((volatile uint32_t*)NVIC_ISER2); volatile uint32_t* pNVIC_ISER3= ((volatile uint32_t*)NVIC_ISER3); #define NVIC_ICER0 0xE000E180U #define NVIC_ICER1 0xE000E184U #define NVIC_ICER2 0xE000E188U #define NVIC_ICER3 0xE000E18CU volatile uint32_t* pNVIC_ICERO= ((volatile uint32_t*)NVIC_ICER0); volatile uint32_t* pNVIC_ICER1= ((volatile uint32_t*)NVIC_ICER1); volatile uint32_t* pNVIC_ICER2= ((volatile uint32_t*)NVIC_ICER2); volatile uint32_t* pNVIC_ICER3= ((volatile uint32_t*)NVIC_ICER3); #define NVIC_PR_BASEADDR 0xE000E400U volatile uint32_t* pNVIC_PR_BASEADDR= ((volatile uint32_t*)NVIC_PR_BASEADDR); #define FLASH_BASEADDR 0x08000000U #define SRAM1_BASEADDR 0x20000000U #define SRAM2_BASEADDR 0x20001C00U #define ROM_BASEADDR 0x1FFF0000U #define SRAM SRAM1_BASEADDR #define PERIPH_BASEADDR 0x40000000U #define APB1PERIPH_BASEADDR PERIPH_BASEADDR #define APB2PERIPH_BASEADDR 0x40010000U #define AHB1PERIPH_BASEADDR 0x40020000U #define AHB2PERIPH_BASEADDR 0x50000000U //#define SYSCFG_BASEADDR 0x40013800U //#define EXTI_BASEADDR 0x40013C00U #define GPIOA_BASEADDR (AHB1PERIPH_BASEADDR + 0x0000) #define GPIOB_BASEADDR (AHB1PERIPH_BASEADDR + 0x0400) #define GPIOC_BASEADDR (AHB1PERIPH_BASEADDR + 0x0800) #define GPIOD_BASEADDR (AHB1PERIPH_BASEADDR + 0x0C00) #define GPIOE_BASEADDR (AHB1PERIPH_BASEADDR + 0x1000) #define GPIOF_BASEADDR (AHB1PERIPH_BASEADDR + 0x1400) #define GPIOG_BASEADDR (AHB1PERIPH_BASEADDR + 0x1800) #define GPIOH_BASEADDR (AHB1PERIPH_BASEADDR + 0x1C00) #define GPIOI_BASEADDR (AHB1PERIPH_BASEADDR + 0x2000) #define RCC_BASEADDR (AHB1PERIPH_BASEADDR + 0x3800) #define I2C1_BASEADDR (APB1PERIPH_BASEADDR + 0x5400) #define I2C2_BASEADDR (APB1PERIPH_BASEADDR + 0x5800) #define I2C3_BASEADDR (APB1PERIPH_BASEADDR + 0x5C00) #define SPI2_BASEADDR (APB1PERIPH_BASEADDR + 0x3800) #define SPI3_BASEADDR (APB1PERIPH_BASEADDR + 0x3C00) #define USART2_BASEADDR (APB1PERIPH_BASEADDR + 0x4400) #define USART3_BASEADDR (APB1PERIPH_BASEADDR + 0x4800) #define UART4_BASEADDR (APB1PERIPH_BASEADDR + 0x4C00) #define UART5_BASEADDR (APB1PERIPH_BASEADDR + 0x5000) #define EXTI_BASEADDR (APB2PERIPH_BASEADDR + 0x3C00) #define SPI1_BASEADDR (APB2PERIPH_BASEADDR + 0x3000) #define SYSCFG_BASEADDR (APB2PERIPH_BASEADDR + 0x3800) #define USART1_BASEADDR (APB2PERIPH_BASEADDR + 0x1000) #define USART6_BASEADDR (APB2PERIPH_BASEADDR + 0x1400) typedef struct { volatile uint32_t MODER; volatile uint32_t OTYPER; volatile uint32_t OSPEEDR; volatile uint32_t PUPDR; volatile uint32_t IDR; volatile uint32_t ODR; volatile uint32_t BSRR; volatile uint32_t LCKR; volatile uint32_t AFRL; volatile uint32_t AFRH; }GPIO_RegDef_t; #define GPIOA ((GPIO_RegDef_t*)GPIOA_BASEADDR) #define GPIOB ((GPIO_RegDef_t*)GPIOB_BASEADDR) #define GPIOC ((GPIO_RegDef_t*)GPIOC_BASEADDR) #define GPIOD ((GPIO_RegDef_t*)GPIOD_BASEADDR) #define GPIOE ((GPIO_RegDef_t*)GPIOE_BASEADDR) #define GPIOF ((GPIO_RegDef_t*)GPIOF_BASEADDR) #define GPIOG ((GPIO_RegDef_t*)GPIOG_BASEADDR) #define GPIOH ((GPIO_RegDef_t*)GPIOH_BASEADDR) #define GPIOI ((GPIO_RegDef_t*)GPIOI_BASEADDR) #define RCC ((RCC_RegDef_t*)RCC_BASEADDR) GPIO_RegDef_t *pGPIOA= GPIOA; GPIO_RegDef_t *pGPIOB= GPIOB; GPIO_RegDef_t *pGPIOC= GPIOC; GPIO_RegDef_t *pGPIOD= GPIOD; GPIO_RegDef_t *pGPIOE= GPIOE; GPIO_RegDef_t *pGPIOF= GPIOF; GPIO_RegDef_t *pGPIOG= GPIOG; GPIO_RegDef_t *pGPIOH= GPIOH; GPIO_RegDef_t *pGPIOI= GPIOI; typedef struct { volatile uint32_t CR; volatile uint32_t PLLCFGR; volatile uint32_t CFGR; volatile uint32_t CIR; volatile uint32_t AHB1RSTR; volatile uint32_t AHB2RSTR; volatile uint32_t AHB3RSTR; uint32_t RESERVED0; volatile uint32_t APB1RSTR; volatile uint32_t APB2RSTR; uint32_t RESERVED1[2]; volatile uint32_t AHB1ENR; volatile uint32_t AHB2ENR; volatile uint32_t AHB3ENR; uint32_t RESERVED2; volatile uint32_t APB1ENR; volatile uint32_t APB2ENR; uint32_t RESERVED3[2]; volatile uint32_t AHB1LPENR; volatile uint32_t AHB2LPENR; volatile uint32_t AHB3LPENR; uint32_t RESERVED4; volatile uint32_t APB1LPENR; volatile uint32_t APB2LPENR; uint32_t RESERVED5[2]; volatile uint32_t BDCR; volatile uint32_t CSR; uint32_t RESERVED6[2]; volatile uint32_t SSCGR; volatile uint32_t PLLI2SCFGR; volatile uint32_t PLLSAICFGR; volatile uint32_t DCKCFGR; volatile uint32_t CKGATENR; volatile uint32_t DCKCFGR2; }RCC_RegDef_t; RCC_RegDef_t *pRCC= RCC; typedef struct { volatile uint32_t MEMRMP; volatile uint32_t PMC; volatile uint32_t EXTICR1; volatile uint32_t EXTICR2; volatile uint32_t EXTICR3; volatile uint32_t EXTICR4; uint32_t RESERVED1[2]; volatile uint32_t CMPCR; }SYSCFG_RegDef_t; SYSCFG_RegDef_t *pSYSCFG= ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR); #define SYSCFG ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR) typedef struct { volatile uint32_t IMR; volatile uint32_t EMR; volatile uint32_t RTSR; volatile uint32_t FTSR; volatile uint32_t SWIER; volatile uint32_t PR; }EXTI_RegDef_t; EXTI_RegDef_t *pEXTI= ((EXTI_RegDef_t*)EXTI_BASEADDR); #define EXTI ((EXTI_RegDef_t*)EXTI_BASEADDR) #endif /* INC_STM32F407XX_H_ */

So this header file contains all the definitions we need to create our main C file.

The contents of the main.c file is shown below.


#include "stm32f407xx.h" int main(void) { //Turns on the clock for GPIO Port A pRCC->AHB1ENR |= (1 << 0); //Turns on the clock for the SYSCFG register pRCC->APB2ENR |= (1 << 14); //Selects GPIO Port Pin 0 as an External Interrupt pSYSCFG->EXTICR1 &= ~(0xF << 0); //Sets Pin 0 to be triggered on the falling edge pEXTI->FTSR |= (1 << 0); //Makes sure that Pin 0 is not triggered on the rising edge pEXTI->RTSR &= ~(1 << 0); //Enable interrupt on pin 0 pEXTI->IMR |= (1 << 0); //Enable the interrupt for EXTI0 on the processor side *pNVIC_ISERO |= (1 << IRQ_NO_EXTI0); //Sets the priority of the interrupt on the processor side *(pNVIC_PR_BASEADDR +(IRQ_NO_EXTI0/4)) |= (2 << (8 *(IRQ_NO_EXTI0 % 4) + 4)); //Sets GPIO Port A Pin 1 to be an output to power on an LED pGPIOA->MODER |= (1 << 2); //Sets GPIO Port A Pin 0 to be of high speed pGPIOA->OSPEEDR |= (0x2 << 0); //Sets GPIO Port A pin 0 to be connected to a pull up resistor pGPIOA->PUPDR |= (1 << 0); //loops forever while(1); } void delay(void) { //Creates a delay of about 400ms for(uint32_t i=0; i < 500000; i++); } void EXTI0_IRQHandler(void){ //handles the interrupt delay(); if(pEXTI->PR & (1 << 0)) { pEXTI->PR |= (1 << 0); } //Toggle the Output LED pGPIOA->ODR= pGPIOA->ODR ^ (1 << 1); }

The first thing we must do is include the header file in our main.c file.

We next have our main function.

In our main function, the first thing we do is enable the peripheral clocks for the GPIO Port A and the SYSCFG register. The GPIO Port A pin 0 is where we will have the source of our external interrupt through a push button connected to it. We must turn on the SYSCFG register because it selects pin 0 to be an external interrupt.

So in order to use a GPIO pin as an external interrupt, we must set it in the SYSCFG register. This process is a little involved. To find an another article dedicated to this, see How to select a GPIO pin to be the source input of an external interrupt in an STM32F407GG Board in C.

To set GPIO port A pin 0 as the source of an external interrupt, we set register EXTICR1 bits 0-3 as 0000.

So what we do next is make pin 0 of the FTSR register a logic HIGH, which makes the interrupt triggered at the falling edge of the signal.

This EXTI FTSR register is shown below.

We want to make sure that rising edge isn't triggered also, so we clear the 0 bit of the RTSR register.

The EXTI RTSR register is shown below.

We then enable the interrupt by setting pin 0 to a logic HIGH in the IMR register, or interrupt mask register. The interrupt mask register allows us to enable or disable external interrupts for the GPIO pins.

The EXTI IMR register is shown below.

Next we have to enable the interrupt for EXTI0 on the processor side. We do this by setting the appropriate bit in the Interrupt Set-enable register. So we just before enabled the interrupt on the microcontroller peripheral side. Now in order for the processor to take in the interrupt, we must enable it on the processor end. We do this by modifying the NVIC_ISER0 register; we write a logic HIGH to the 6th bit of this register.

The Interrupt Set-enable Registers are shown in the diagram below.

One thing that is important to know that for the Interrupt set-enable registers is that there are 8 of these registers in total, ISER0-ISER7.

Each register is 32 bits, which means for the 8 registers, they compose 256 bits, which covers all possible 240 external interrupts that the Cortex-M4 processor can process.

Each bit refers to 1 of the possible external interrupts corresponding to the IRQ number of the interrupt.

So for the first register of the Interrupt Set-enable registers, ISER0, this addresses the external interrupts IRQ 0 to IRQ 31.

ISER1 corresponds to interrupts IRQ 32 to 63.

ISER2 corresponds to interrupts IRQ 64 to 93.

In our case, we want to enable the external interrupt, IRQ 6, which is ISER0 register bit 6; so we set this bit to 1.

The next step is optional.

In the next step, we set the priority of the external interrupt.

This is important if you have multiple interrupts and want to prioritize one or some over others.

This is done on the processor side with the interrupt priority registers. The interrupt priority registers consist of 60 registers in total that can set the interrupt priority of 240 external interrupts based on the IRQ number of the interrupt.

If you look at the vector table for the STM32F407G microcontroller in its datasheet, you will see that there are only 82 external interrupts possible for this microcontroller.

So it doesn't use the full capability that the processor can offer.

So each of the 60 registers are 32 bits.

This is shown in the diagram below.

Each register is divided into 4 8-bit sections to cover the 240 possible external interrupts.

These registers are IPR0 to IPR59.

Register IPR0 sets the priorities for IRQ 0, IRQ 1, IRQ 2, and IRQ 3.

The first 8 bits are for IRQ 0.

The next 8 bits are for IRQ 1.

The next 8 bits are for IRQ 2.

And the last 8 bits of the 32 bits are for IRQ 3.

Register IPR1 sets the priorities for IRQ 4, IRQ 5, IRQ 6, and IRQ 7.

And so on.

To know which register you need to be working with when dealing with a particular IRQ number, take the IRQ number and divide it by 4. In this case of IRQ 6, 6/4 = 1. Therefore, we need to deal with register IPR1.

Now in order to know which 8-bit section you need to modify, you take the IRQ number and use the modulus operator on it. 6%4= 2. Therefore, we write to the 3rd 8-bit section of the IPR1 register.

Being that we are working with IRQ 6 in our code, we need to modify the register IPR1 in bits 16-23.

Let's now break down the formula, *(pNVIC_PR_BASEADDR +(IRQ_NO_EXTI0/4)) |= (2 << (8 *(IRQ_NO_EXTI0 % 4) + 4));

So we defined the base address of the priority register in the macro, pNVIC_PR_BASEADDR

The base address is, 0xE000E400U

The IRQ number is 6; therefore, 6/4 = 1 in integer mathematics. We add 1 to the base address, which adds 4 bytes to the address. This gives us the address of 0xE000E404U, which is the address of register IPR1.

So now the pointer variable is referring to register, IPR1.

We then set the priority value of 2 to the 8 times the value of 6%4, and then we add 4 to this value.

To understand this, multiplying the value by 8 gives us the start of the 8-bit section of the register.

The reason we add 4 to this register is that the value of the priority is set by setting the upper 4 bits of the 8 bits. The lower 4 bits are ignored.

The priority levels we can set ranges in value from 0 to 15. The lower the number, the greater the priority, so a priority value of 0 is the highest priority.

15 in binary is 4 digits, 1111

Therefore, only 4 bits are needed to set the priority and it is the upper 4 bits of the 8-bit section.

So after this, we set GPIO port A pin 1 to be an output. We do this by writing a 1 to bit 2 of the GPIO mode register.

We set GPIO port A pin 0 to be of high speed.

We then enable the internal pull up resistor on GPIOA port A pin 0. This makes the push button pulled up to VDD when not pressed. When it is pressed, it will be brought down to VSS, or GND.

This GPIO port pull-up/pull-down (PUPDR) is shown in the diagram below.

So with an internal pull-up resistor, we do not have to connect an external resistor, saving parts.

We then have the program loop forever with the statement, while(1);

After this main() function, we then create a delay() function, because we need to eliminate debouncing with the button press. We can do this in software. In hardware, you could use capacitors. In software, you just create a delay() function. The delay() function we create gives a delay of about 400ms or 4/10th of a second. This prevents multiple keypresses from being detected within a short period of time.

Next, we have our interrupt service routine, or ISR.

This is what is done when the external interrupt is triggered.

We use the delay() function to prevent debouncing.

The next thing we have to do is clear bit 0 in the pending register.

The EXTI pending register is shown below.

So when an external interrupt is triggered by the falling edge of the signal, what happens is the pending register of the EXTI registers is set to 1.

What we must do now is clear this bit. If this bit is not clear, the external interrupt, once triggered, stays triggered. To allow the interrupt to execute only once, we must clear the bit in the interrupt service routine. The bit is cleared by setting the bit to 1.

Lastly, we use XOR logic to toggle the LED connected to GPIO port A pin 1 with the line, pGPIOA->ODR= pGPIOA->ODR ^ (1 << 1);

So running this program, the LED will toggle from on to off or off to on with each button press.

Each button press triggers an external interrupt.

So this is how to enable a GPIO pin to function as the source of an external interrupt with the STM32F407G microcontroller board in C.

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