How to Toggle an LED with a Timer in Output Compare Mode in an STM32F446 Microcontroller Board in C

In this article, we show how to toggle an LED with a timer in output compare mode in an STM32F446 microcontroller board in C.

So, in this project, we are going to use a general-purpose timer, specifically timer 2 (TIM2).

We are going to set this general-purpose timer to be in output compare mode.

What output compare mode does is it creates a waveform at the output, such as pulse lasting for a certain duration that you set. The mode that we can select can include toggle mode or it can be PWM mode, amongst others.

In this project, we will set the output compare 1 mode to toggle, because we want to toggle an LED.

If you were doing a project such as driving a motor, we may use PWM mode.

But the basic principle is it causes an output waveform from the timer that we can then force onto a GPIO pin to power on a load.

So a general-purpose timer in STM32 boards have various channels as outputs.

The timer we are working with in this case is timer 2. It has 4 output channels.

So this means is that we can generate a waveform from timer 2 and this waveform can then be output to any of the various channels of this timer.

In case, you are wondering which pins are the channels for timer 2, you can find this in the Alternate Function Mapping of GPIO Port A.

This is shown below.

Looking at this table, you can see that PA0, PA5, and PA15 can all act as TIM2_CH1.

PA1 can function as TIM2_CH2

PA2 can function as TIM2_CH3

PA3 can function as TIM2_CH4

If there pins are configured for alternate function mode AF1, then we can project the timer's output onto these pins, so that these pins receive the waveform generated by the timer.

So being a channel of a timer is an alternate function of a GPIO pin.

In this project, we will use pin PA5, because it has an onboard LED, which is what we will configure to toggle.

We need 2 major code files in order for this code to work.

We need our header file, which contains many macros and structures that describe the various registers and needed values.

We then need our main C file, which contains the code that puts timer 2 in output compare mode in a toggle state so that it can toggle an LED on and off every 1 second.

Below is the header file, which we name stm32f407xx.h


/* * stm32f446.h * * Created on: May 6, 2022 * Author: dlhyl */ #ifndef STM32F446_H_ #define STM32F446_H_ #include <stdint.h> #define __vo volatile #define IRQ_NO_EXTI0 6 #define IRQ_NO_EXTI1 7 #define IRQ_NO_EXTI2 8 #define IRQ_NO_EXTI3 9 #define IRQ_NO_EXTI4 10 #define IRQ_NO_EXTI9_5 23 #define IRQ_NO_EXTI15_10 40 //Processor specific details #define NVIC_ISER0 0xE000E100U #define NVIC_ISER1 0xE000E104U #define NVIC_ISER2 0xE000E108U #define NVIC_ISER3 0xE000E10CU volatile uint32_t* pNVIC_ISER0= ((volatile uint32_t*)NVIC_ISER0); volatile uint32_t* pNVIC_ISER1= ((volatile uint32_t*)NVIC_ISER1); volatile uint32_t* pNVIC_ISER2= ((volatile uint32_t*)NVIC_ISER2); volatile uint32_t* pNVIC_ISER3= ((volatile uint32_t*)NVIC_ISER3); #define NVIC_ICER0 0xE000E180U #define NVIC_ICER1 0xE000E184U #define NVIC_ICER2 0xE000E188U #define NVIC_ICER3 0xE000E18CU volatile uint32_t* pNVIC_ICERO= ((volatile uint32_t*)NVIC_ICER0); volatile uint32_t* pNVIC_ICER1= ((volatile uint32_t*)NVIC_ICER1); volatile uint32_t* pNVIC_ICER2= ((volatile uint32_t*)NVIC_ICER2); volatile uint32_t* pNVIC_ICER3= ((volatile uint32_t*)NVIC_ICER3); #define NVIC_PR_BASEADDR 0xE000E400U volatile uint32_t* pNVIC_PR_BASEADDR= ((volatile uint32_t*)NVIC_PR_BASEADDR); #define SYS_FREQ 16000000U #define APB1_CLK SYS_FREQ #define USART_BAUDRATE 115200 #define FLASH_BASEADDR 0x08000000U #define SRAM1_BASEADDR 0x20000000U #define SRAM2_BASEADDR 0x20001C00U #define ROM_BASEADDR 0x1FFF0000U #define SRAM SRAM1_BASEADDR #define PERIPH_BASEADDR 0x40000000U #define APB1PERIPH_BASEADDR PERIPH_BASEADDR #define APB2PERIPH_BASEADDR 0x40010000U #define AHB1PERIPH_BASEADDR 0x40020000U #define AHB2PERIPH_BASEADDR 0x50000000U //#define SYSCFG_BASEADDR 0x40013800U //#define EXTI_BASEADDR 0x40013C00U #define GPIOA_BASEADDR (AHB1PERIPH_BASEADDR + 0x0000) #define GPIOB_BASEADDR (AHB1PERIPH_BASEADDR + 0x0400) #define GPIOC_BASEADDR (AHB1PERIPH_BASEADDR + 0x0800) #define GPIOD_BASEADDR (AHB1PERIPH_BASEADDR + 0x0C00) #define GPIOE_BASEADDR (AHB1PERIPH_BASEADDR + 0x1000) #define GPIOF_BASEADDR (AHB1PERIPH_BASEADDR + 0x1400) #define GPIOG_BASEADDR (AHB1PERIPH_BASEADDR + 0x1800) #define GPIOH_BASEADDR (AHB1PERIPH_BASEADDR + 0x1C00) #define GPIOI_BASEADDR (AHB1PERIPH_BASEADDR + 0x2000) #define RCC_BASEADDR (AHB1PERIPH_BASEADDR + 0x3800) #define I2C1_BASEADDR (APB1PERIPH_BASEADDR + 0x5400) #define I2C2_BASEADDR (APB1PERIPH_BASEADDR + 0x5800) #define I2C3_BASEADDR (APB1PERIPH_BASEADDR + 0x5C00) #define SPI2_BASEADDR (APB1PERIPH_BASEADDR + 0x3800) #define SPI3_BASEADDR (APB1PERIPH_BASEADDR + 0x3C00) #define USART2_BASEADDR (APB1PERIPH_BASEADDR + 0x4400) #define USART3_BASEADDR (APB1PERIPH_BASEADDR + 0x4800) #define UART4_BASEADDR (APB1PERIPH_BASEADDR + 0x4C00) #define UART5_BASEADDR (APB1PERIPH_BASEADDR + 0x5000) #define TIM2_BASEADDR (APB1PERIPH_BASEADDR + 0x0000) #define TIM3_BASEADDR (APB1PERIPH_BASEADDR + 0x0400) #define TIM4_BASEADDR (APB1PERIPH_BASEADDR + 0x0800) #define TIM5_BASEADDR (APB1PERIPH_BASEADDR + 0x0C00) #define EXTI_BASEADDR (APB2PERIPH_BASEADDR + 0x3C00) #define SPI1_BASEADDR (APB2PERIPH_BASEADDR + 0x3000) #define SPI4_BASEADDR (APB2PERIPH_BASEADDR + 0x3400) #define SYSCFG_BASEADDR (APB2PERIPH_BASEADDR + 0x3800) #define USART1_BASEADDR (APB2PERIPH_BASEADDR + 0x1000) #define USART6_BASEADDR (APB2PERIPH_BASEADDR + 0x1400) #define SPI5_BASEADDR (APB2PERIPH_BASEADDR + 0x5000) #define SPI6_BASEADDR (APB2PERIPH_BASEADDR + 0x5400) typedef struct { volatile uint32_t MODER; volatile uint32_t OTYPER; volatile uint32_t OSPEEDR; volatile uint32_t PUPDR; volatile uint32_t IDR; volatile uint32_t ODR; volatile uint32_t BSRR; volatile uint32_t LCKR; volatile uint32_t AFRL; volatile uint32_t AFRH; }GPIO_RegDef_t; #define GPIOA ((GPIO_RegDef_t*)GPIOA_BASEADDR) #define GPIOB ((GPIO_RegDef_t*)GPIOB_BASEADDR) #define GPIOC ((GPIO_RegDef_t*)GPIOC_BASEADDR) #define GPIOD ((GPIO_RegDef_t*)GPIOD_BASEADDR) #define GPIOE ((GPIO_RegDef_t*)GPIOE_BASEADDR) #define GPIOF ((GPIO_RegDef_t*)GPIOF_BASEADDR) #define GPIOG ((GPIO_RegDef_t*)GPIOG_BASEADDR) #define GPIOH ((GPIO_RegDef_t*)GPIOH_BASEADDR) #define GPIOI ((GPIO_RegDef_t*)GPIOI_BASEADDR) #define RCC ((RCC_RegDef_t*)RCC_BASEADDR) GPIO_RegDef_t *pGPIOA= GPIOA; GPIO_RegDef_t *pGPIOB= GPIOB; GPIO_RegDef_t *pGPIOC= GPIOC; GPIO_RegDef_t *pGPIOD= GPIOD; GPIO_RegDef_t *pGPIOE= GPIOE; GPIO_RegDef_t *pGPIOF= GPIOF; GPIO_RegDef_t *pGPIOG= GPIOG; GPIO_RegDef_t *pGPIOH= GPIOH; GPIO_RegDef_t *pGPIOI= GPIOI; typedef struct { volatile uint32_t CR; volatile uint32_t PLLCFGR; volatile uint32_t CFGR; volatile uint32_t CIR; volatile uint32_t AHB1RSTR; volatile uint32_t AHB2RSTR; volatile uint32_t AHB3RSTR; uint32_t RESERVED0; volatile uint32_t APB1RSTR; volatile uint32_t APB2RSTR; uint32_t RESERVED1[2]; volatile uint32_t AHB1ENR; volatile uint32_t AHB2ENR; volatile uint32_t AHB3ENR; uint32_t RESERVED2; volatile uint32_t APB1ENR; volatile uint32_t APB2ENR; uint32_t RESERVED3[2]; volatile uint32_t AHB1LPENR; volatile uint32_t AHB2LPENR; volatile uint32_t AHB3LPENR; uint32_t RESERVED4; volatile uint32_t APB1LPENR; volatile uint32_t APB2LPENR; uint32_t RESERVED5[2]; volatile uint32_t BDCR; volatile uint32_t CSR; uint32_t RESERVED6[2]; volatile uint32_t SSCGR; volatile uint32_t PLLI2SCFGR; volatile uint32_t PLLSAICFGR; volatile uint32_t DCKCFGR; volatile uint32_t CKGATENR; volatile uint32_t DCKCFGR2; }RCC_RegDef_t; RCC_RegDef_t *pRCC= RCC; typedef struct { volatile uint32_t MEMRMP; volatile uint32_t PMC; volatile uint32_t EXTICR1; volatile uint32_t EXTICR2; volatile uint32_t EXTICR3; volatile uint32_t EXTICR4; uint32_t RESERVED1[2]; volatile uint32_t CMPCR; }SYSCFG_RegDef_t; SYSCFG_RegDef_t *pSYSCFG= ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR); #define SYSCFG ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR) typedef struct { volatile uint32_t IMR; volatile uint32_t EMR; volatile uint32_t RTSR; volatile uint32_t FTSR; volatile uint32_t SWIER; volatile uint32_t PR; }EXTI_RegDef_t; EXTI_RegDef_t *pEXTI= ((EXTI_RegDef_t*)EXTI_BASEADDR); #define EXTI ((EXTI_RegDef_t*)EXTI_BASEADDR) typedef struct { volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t SR; volatile uint32_t DR; volatile uint32_t CRCPR; volatile uint32_t RXCRCR; volatile uint32_t TXCRCR; volatile uint32_t I2SCFGR; volatile uint32_t I2SPR; }SPI_RegDef_t; SPI_RegDef_t *pSPI1= ((SPI_RegDef_t*)SPI1_BASEADDR); SPI_RegDef_t *pSPI2= ((SPI_RegDef_t*)SPI2_BASEADDR); SPI_RegDef_t *pSPI3= ((SPI_RegDef_t*)SPI3_BASEADDR); SPI_RegDef_t *pSPI4= ((SPI_RegDef_t*)SPI4_BASEADDR); SPI_RegDef_t *pSPI5= ((SPI_RegDef_t*)SPI5_BASEADDR); SPI_RegDef_t *pSPI6= ((SPI_RegDef_t*)SPI6_BASEADDR); #define SPI1 ((SPI_RegDef_t*)SPI1_BASEADDR) #define SPI2 ((SPI_RegDef_t*)SPI2_BASEADDR) #define SPI3 ((SPI_RegDef_t*)SPI3_BASEADDR) #define SPI4 ((SPI_RegDef_t*)SPI4_BASEADDR) #define SPI5 ((SPI_RegDef_t*)SPI5_BASEADDR) #define SPI6 ((SPI_RegDef_t*)SPI6_BASEADDR) typedef struct { volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t OAR1; volatile uint32_t OAR2; volatile uint32_t DR; volatile uint32_t SR1; volatile uint32_t SR2; volatile uint32_t CCR; volatile uint32_t TRISE; volatile uint32_t FLTR; }I2C_RegDef_t; I2C_RegDef_t *pI2C1= ((I2C_RegDef_t*)I2C1_BASEADDR); I2C_RegDef_t *pI2C2= ((I2C_RegDef_t*)I2C2_BASEADDR); I2C_RegDef_t *pI2C3= ((I2C_RegDef_t*)I2C3_BASEADDR); #define I2C1 ((I2C_RegDef_t*)I2C1_BASEADDR) #define I2C2 ((I2C_RegDef_t*)I2C2_BASEADDR) #define I2C3 ((I2C_RegDef_t*)I2C3_BASEADDR) typedef struct { volatile uint32_t SR; volatile uint32_t DR; volatile uint32_t BRR; volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t CR3; volatile uint32_t GTPR; }USART_RegDef_t; USART_RegDef_t *pUSART1= ((USART_RegDef_t*)USART1_BASEADDR); USART_RegDef_t *pUSART2= ((USART_RegDef_t*)USART2_BASEADDR); USART_RegDef_t *pUSART3= ((USART_RegDef_t*)USART3_BASEADDR); USART_RegDef_t *pUART4= ((USART_RegDef_t*)UART4_BASEADDR); USART_RegDef_t *pUART5= ((USART_RegDef_t*)UART5_BASEADDR); USART_RegDef_t *pUSART6= ((USART_RegDef_t*)USART6_BASEADDR); #define USART1 ((USART_RegDef_t*)USART1_BASEADDR) #define USART2 ((USART_RegDef_t*)USART2_BASEADDR) #define USART3 ((USART_RegDef_t*)USART3_BASEADDR) #define USART4 ((USART_RegDef_t*)UART4_BASEADDR) #define USART5 ((USART_RegDef_t*)UART5_BASEADDR) #define USART6 ((USART_RegDef_t*)USART6_BASEADDR) typedef struct { volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t SMCR; volatile uint32_t DIER; volatile uint32_t SR; volatile uint32_t EGR; volatile uint32_t CCMR1; volatile uint32_t CCMR2; volatile uint32_t CCER; volatile uint32_t CNT; volatile uint32_t PSC; volatile uint32_t ARR; uint32_t RESERVED0; volatile uint32_t CCR1; volatile uint32_t CCR2; volatile uint32_t CCR3; volatile uint32_t CCR4; uint32_t RESERVED1; volatile uint32_t DCR; volatile uint32_t DMAR; volatile uint32_t OR; }TIM_RegDef_t; TIM_RegDef_t *pTIM2= ((TIM_RegDef_t*)TIM2_BASEADDR); TIM_RegDef_t *pTIM3= ((TIM_RegDef_t*)TIM3_BASEADDR); TIM_RegDef_t *pTIM4= ((TIM_RegDef_t*)TIM4_BASEADDR); TIM_RegDef_t *pTIM5= ((TIM_RegDef_t*)TIM5_BASEADDR); #define TIM2 ((TIM_RegDef_t*)TIM2_BASEADDR) #define TIM3 ((TIM_RegDef_t*)TIM3_BASEADDR) #define TIM4 ((TIM_RegDef_t*)TIM4_BASEADDR) #define TIM5 ((TIM_RegDef_t*)TIM5_BASEADDR) #endif /* STM32F446_H_ */

The contents of the main.c file is shown below.


#include <stdint.h> #include "stm32f446.h" void tim2_pa5_output_compare(void); int main(void) { tim2_pa5_output_compare(); } void tim2_pa5_output_compare(void) { //Turn on peripheral clock for GPIO Port A pRCC->AHB1ENR |= (1 << 0); //Sets PA5 in alternate function mode pGPIOA->MODER |= (0b10 << 10); //Sets PA5 to alternate function mode to act as TIM2_CH1 (AF1) pGPIOA->AFRL |= (0b0001 << 20); //Enable clock access to tim2 pRCC->APB1ENR |= (1 << 0); //Set the prescaler value pTIM2->PSC = 16000-1; //Set auto-reload value pTIM2->ARR = 1000 -1; //Sets Output compare to toggle mode pTIM2->CCMR1 |= (0b011 << 4); //Enable tim2 ch1 in compare mode pTIM2->CCER |= (1 << 0); //Clear the counter pTIM2->CNT= 0; //Enable the timer pTIM2->CR1 |= (1 << 0); }

The first thing we must do is include the stdint.h header file and our stm32f446xx.h header file in our main.c file.

We create a function protoytpe for our tim2_pa5_output_compare() function, so that the compiler knows its return type, what arguments it accepts, along with its data type.

We then have our main() function, which simply consists of the timer function we have created.

So now we go to our timer function, which sets up the timer 2 in output capture mode.

In our timer function, the first thing we do is turn on the peripheral clock for the GPIO Port A, because pin PA5 is the pin we configure to be the timer channel we will use, which is TIM2_CH1

We then put pin PA5 in alternate function mode in the GPIO mode register.

We then use the AFRL register and set pin PA5 to function as TIM2_CH1, which is AF1.

Next, we enable the clock for the timer 2. The bus connected to the timer, TIM2, is the APB1 bus.

Next, we set the prescaler of the timer and the ARR, so that we get a signal of 1Hz, so that we have the LED turn off and on every 1 second.

Next, we go to the TIMx capture/compare mode register 1.

Within this register, we can specify that we want the compare mode to be Toggle.

The register is shown below.

In the OC1M bits, bits 6:4, we set the mode to Toggle by setting these bits to 011.

We then now go to the TIMx capture/compare enable register, where we set channel 1 as the output channel that we want to use.

This register is shown below.

We write a 1 to bit 0, CC1E. Doing this makes channel 1 an output.

Remember that we are using TIM2_CH1.

In this register, you see 4 channels avaiable, because each timer has 4 channels. We have to select which channel we want to enable, which in this case is channel 1.

We then clear the timer counter register, so that is has no residual count.

We then enable the timer counter and start the process.

You should see that the onboard LED turns on and off each second.

This is the effect of the timer being in output compare mode, where it generates a toggling waveform, which feeds into pin PA5 to toggle the LED on and off.

This is one example of output compare mode.

So this is how we can toggle an LED on and off using the timer output compare mode in an STM32F446 microcontroller board in C.

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