How to Transmit Data from Direct Memory Access (DMA) to a Peripheral Device with an STM32F446 Microcontroller Board in C

In this article, we show how to transmit data from Direct Memory Access (DMA) to a peripheral device with an STM32F446 microcontroller board in C.

Direct Memory Access (DMA) allows data transfers to take place in the background without the intervention of the Cortex-M processor. During this operation, the main processor can execute other tasks and it is only interrupted when a whole data block is available for processing. Therefore, large amounts of data can be transferred with no major impact on system performance.

So it is called direct memory access, because it can go directly to a peripheral device or memory as needed.

Whenever large amounts of data need to be transferred without desiring any drop in system performance, DMA can be a good solution.

According to the datasheet, Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory and between memory and memory. Data can be quickly moved by DMA without any CPU action. This keeps CPU resources free for other operations. The DMA controller combines a powerful dual AHB master bus architecture with independent FIFO to optimize the bandwidth of the system, based on a complex bus matrix architecture.

The STM32F446 microcontroller board has 2 DMA controllers (DMA1 and DMA2), which can be used for direct memory access.

Each DMA controller has 8 streams, and each of the streams has 8 channels. Therefore, each DMA controller has a possible 64 different configurations.

Whether you use DMA1 or DMA2 depends on which peripheral device you are working with.

For example, in our program, we stated that we want to use UART communication to send data from DMA to a peripheral device. Therefore, we need to configure a USART_TX pin. We do this for USART2_TX

There is something referred to as a DMA request mapping, which allows us to know which stream and which channel produces a certain configuration.

Look at the DMA requesting mapping below for DMA1 and DMA2.

Looking at the DMA1 request mapping, you can see that if we select Stream 6 and Channel 4, we will have selected USART2_TX.

With this pin (with proper configuration), we can send data from DMA to a peripheral device via USART (or UART) communicadtion.

In this program, we will simply send data from direct memory access to RealTerm software using the UART communication protocol.

We transfer the data from the STM32 board to our computer via USB. With the particular pin of the STM32 board that we use as UART, the USB can carry the UART communication through its medium. There, for this program, we need very limited hardware, just the STM32 board, our computer, and the USB connection.

We need 2 major code files in order for this code to work.

We need our header file, which contains many macros and structures that describe the various registers and needed values.

We then need our main C file, which contains the code that allows us to transfer

Below is the header file that we will need for our code, which in this case is named, stm32f446.h


/* * stm32f446.h * * Created on: May 6, 2022 * Author: dlhyl */ #ifndef STM32F446_H_ #define STM32F446_H_ #include <stdint.h> #define __vo volatile #define IRQ_NO_EXTI0 6 #define IRQ_NO_EXTI1 7 #define IRQ_NO_EXTI2 8 #define IRQ_NO_EXTI3 9 #define IRQ_NO_EXTI4 10 #define IRQ_NO_EXTI9_5 23 #define IRQ_NO_EXTI15_10 40 //Processor specific details #define NVIC_ISER0 0xE000E100U #define NVIC_ISER1 0xE000E104U #define NVIC_ISER2 0xE000E108U #define NVIC_ISER3 0xE000E10CU volatile uint32_t* pNVIC_ISER0= ((volatile uint32_t*)NVIC_ISER0); volatile uint32_t* pNVIC_ISER1= ((volatile uint32_t*)NVIC_ISER1); volatile uint32_t* pNVIC_ISER2= ((volatile uint32_t*)NVIC_ISER2); volatile uint32_t* pNVIC_ISER3= ((volatile uint32_t*)NVIC_ISER3); #define NVIC_ICER0 0xE000E180U #define NVIC_ICER1 0xE000E184U #define NVIC_ICER2 0xE000E188U #define NVIC_ICER3 0xE000E18CU volatile uint32_t* pNVIC_ICERO= ((volatile uint32_t*)NVIC_ICER0); volatile uint32_t* pNVIC_ICER1= ((volatile uint32_t*)NVIC_ICER1); volatile uint32_t* pNVIC_ICER2= ((volatile uint32_t*)NVIC_ICER2); volatile uint32_t* pNVIC_ICER3= ((volatile uint32_t*)NVIC_ICER3); #define NVIC_PR_BASEADDR 0xE000E400U volatile uint32_t* pNVIC_PR_BASEADDR= ((volatile uint32_t*)NVIC_PR_BASEADDR); #define SYS_FREQ 16000000U #define APB1_CLK SYS_FREQ #define USART_BAUDRATE 115200 #define FLASH_BASEADDR 0x08000000U #define SRAM1_BASEADDR 0x20000000U #define SRAM2_BASEADDR 0x20001C00U #define ROM_BASEADDR 0x1FFF0000U #define SRAM SRAM1_BASEADDR #define PERIPH_BASEADDR 0x40000000U #define APB1PERIPH_BASEADDR PERIPH_BASEADDR #define APB2PERIPH_BASEADDR 0x40010000U #define AHB1PERIPH_BASEADDR 0x40020000U #define AHB2PERIPH_BASEADDR 0x50000000U //#define SYSCFG_BASEADDR 0x40013800U //#define EXTI_BASEADDR 0x40013C00U #define GPIOA_BASEADDR (AHB1PERIPH_BASEADDR + 0x0000) #define GPIOB_BASEADDR (AHB1PERIPH_BASEADDR + 0x0400) #define GPIOC_BASEADDR (AHB1PERIPH_BASEADDR + 0x0800) #define GPIOD_BASEADDR (AHB1PERIPH_BASEADDR + 0x0C00) #define GPIOE_BASEADDR (AHB1PERIPH_BASEADDR + 0x1000) #define GPIOF_BASEADDR (AHB1PERIPH_BASEADDR + 0x1400) #define GPIOG_BASEADDR (AHB1PERIPH_BASEADDR + 0x1800) #define GPIOH_BASEADDR (AHB1PERIPH_BASEADDR + 0x1C00) #define GPIOI_BASEADDR (AHB1PERIPH_BASEADDR + 0x2000) #define RCC_BASEADDR (AHB1PERIPH_BASEADDR + 0x3800) #define DMA1_BASEADDR (AHB1PERIPH_BASEADDR + 0x6000) #define DMA2_BASEADDR (AHB1PERIPH_BASEADDR + 0x6400) #define I2C1_BASEADDR (APB1PERIPH_BASEADDR + 0x5400) #define I2C2_BASEADDR (APB1PERIPH_BASEADDR + 0x5800) #define I2C3_BASEADDR (APB1PERIPH_BASEADDR + 0x5C00) #define SPI2_BASEADDR (APB1PERIPH_BASEADDR + 0x3800) #define SPI3_BASEADDR (APB1PERIPH_BASEADDR + 0x3C00) #define USART2_BASEADDR (APB1PERIPH_BASEADDR + 0x4400) #define USART3_BASEADDR (APB1PERIPH_BASEADDR + 0x4800) #define UART4_BASEADDR (APB1PERIPH_BASEADDR + 0x4C00) #define UART5_BASEADDR (APB1PERIPH_BASEADDR + 0x5000) #define EXTI_BASEADDR (APB2PERIPH_BASEADDR + 0x3C00) #define SPI1_BASEADDR (APB2PERIPH_BASEADDR + 0x3000) #define SPI4_BASEADDR (APB2PERIPH_BASEADDR + 0x3400) #define SYSCFG_BASEADDR (APB2PERIPH_BASEADDR + 0x3800) #define USART1_BASEADDR (APB2PERIPH_BASEADDR + 0x1000) #define USART6_BASEADDR (APB2PERIPH_BASEADDR + 0x1400) #define SPI5_BASEADDR (APB2PERIPH_BASEADDR + 0x5000) #define SPI6_BASEADDR (APB2PERIPH_BASEADDR + 0x5400) typedef struct { volatile uint32_t MODER; volatile uint32_t OTYPER; volatile uint32_t OSPEEDR; volatile uint32_t PUPDR; volatile uint32_t IDR; volatile uint32_t ODR; volatile uint32_t BSRR; volatile uint32_t LCKR; volatile uint32_t AFRL; volatile uint32_t AFRH; }GPIO_RegDef_t; #define GPIOA ((GPIO_RegDef_t*)GPIOA_BASEADDR) #define GPIOB ((GPIO_RegDef_t*)GPIOB_BASEADDR) #define GPIOC ((GPIO_RegDef_t*)GPIOC_BASEADDR) #define GPIOD ((GPIO_RegDef_t*)GPIOD_BASEADDR) #define GPIOE ((GPIO_RegDef_t*)GPIOE_BASEADDR) #define GPIOF ((GPIO_RegDef_t*)GPIOF_BASEADDR) #define GPIOG ((GPIO_RegDef_t*)GPIOG_BASEADDR) #define GPIOH ((GPIO_RegDef_t*)GPIOH_BASEADDR) #define GPIOI ((GPIO_RegDef_t*)GPIOI_BASEADDR) #define RCC ((RCC_RegDef_t*)RCC_BASEADDR) GPIO_RegDef_t *pGPIOA= GPIOA; GPIO_RegDef_t *pGPIOB= GPIOB; GPIO_RegDef_t *pGPIOC= GPIOC; GPIO_RegDef_t *pGPIOD= GPIOD; GPIO_RegDef_t *pGPIOE= GPIOE; GPIO_RegDef_t *pGPIOF= GPIOF; GPIO_RegDef_t *pGPIOG= GPIOG; GPIO_RegDef_t *pGPIOH= GPIOH; GPIO_RegDef_t *pGPIOI= GPIOI; typedef struct { volatile uint32_t CR; volatile uint32_t PLLCFGR; volatile uint32_t CFGR; volatile uint32_t CIR; volatile uint32_t AHB1RSTR; volatile uint32_t AHB2RSTR; volatile uint32_t AHB3RSTR; uint32_t RESERVED0; volatile uint32_t APB1RSTR; volatile uint32_t APB2RSTR; uint32_t RESERVED1[2]; volatile uint32_t AHB1ENR; volatile uint32_t AHB2ENR; volatile uint32_t AHB3ENR; uint32_t RESERVED2; volatile uint32_t APB1ENR; volatile uint32_t APB2ENR; uint32_t RESERVED3[2]; volatile uint32_t AHB1LPENR; volatile uint32_t AHB2LPENR; volatile uint32_t AHB3LPENR; uint32_t RESERVED4; volatile uint32_t APB1LPENR; volatile uint32_t APB2LPENR; uint32_t RESERVED5[2]; volatile uint32_t BDCR; volatile uint32_t CSR; uint32_t RESERVED6[2]; volatile uint32_t SSCGR; volatile uint32_t PLLI2SCFGR; volatile uint32_t PLLSAICFGR; volatile uint32_t DCKCFGR; volatile uint32_t CKGATENR; volatile uint32_t DCKCFGR2; }RCC_RegDef_t; RCC_RegDef_t *pRCC= RCC; typedef struct { volatile uint32_t MEMRMP; volatile uint32_t PMC; volatile uint32_t EXTICR1; volatile uint32_t EXTICR2; volatile uint32_t EXTICR3; volatile uint32_t EXTICR4; uint32_t RESERVED1[2]; volatile uint32_t CMPCR; }SYSCFG_RegDef_t; SYSCFG_RegDef_t *pSYSCFG= ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR); #define SYSCFG ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR) typedef struct { volatile uint32_t IMR; volatile uint32_t EMR; volatile uint32_t RTSR; volatile uint32_t FTSR; volatile uint32_t SWIER; volatile uint32_t PR; }EXTI_RegDef_t; EXTI_RegDef_t *pEXTI= ((EXTI_RegDef_t*)EXTI_BASEADDR); #define EXTI ((EXTI_RegDef_t*)EXTI_BASEADDR) typedef struct { volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t SR; volatile uint32_t DR; volatile uint32_t CRCPR; volatile uint32_t RXCRCR; volatile uint32_t TXCRCR; volatile uint32_t I2SCFGR; volatile uint32_t I2SPR; }SPI_RegDef_t; SPI_RegDef_t *pSPI1= ((SPI_RegDef_t*)SPI1_BASEADDR); SPI_RegDef_t *pSPI2= ((SPI_RegDef_t*)SPI2_BASEADDR); SPI_RegDef_t *pSPI3= ((SPI_RegDef_t*)SPI3_BASEADDR); SPI_RegDef_t *pSPI4= ((SPI_RegDef_t*)SPI4_BASEADDR); SPI_RegDef_t *pSPI5= ((SPI_RegDef_t*)SPI5_BASEADDR); SPI_RegDef_t *pSPI6= ((SPI_RegDef_t*)SPI6_BASEADDR); #define SPI1 ((SPI_RegDef_t*)SPI1_BASEADDR) #define SPI2 ((SPI_RegDef_t*)SPI2_BASEADDR) #define SPI3 ((SPI_RegDef_t*)SPI3_BASEADDR) #define SPI4 ((SPI_RegDef_t*)SPI4_BASEADDR) #define SPI5 ((SPI_RegDef_t*)SPI5_BASEADDR) #define SPI6 ((SPI_RegDef_t*)SPI6_BASEADDR) typedef struct { volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t OAR1; volatile uint32_t OAR2; volatile uint32_t DR; volatile uint32_t SR1; volatile uint32_t SR2; volatile uint32_t CCR; volatile uint32_t TRISE; volatile uint32_t FLTR; }I2C_RegDef_t; I2C_RegDef_t *pI2C1= ((I2C_RegDef_t*)I2C1_BASEADDR); I2C_RegDef_t *pI2C2= ((I2C_RegDef_t*)I2C2_BASEADDR); I2C_RegDef_t *pI2C3= ((I2C_RegDef_t*)I2C3_BASEADDR); #define I2C1 ((I2C_RegDef_t*)I2C1_BASEADDR) #define I2C2 ((I2C_RegDef_t*)I2C2_BASEADDR) #define I2C3 ((I2C_RegDef_t*)I2C3_BASEADDR) typedef struct { volatile uint32_t SR; volatile uint32_t DR; volatile uint32_t BRR; volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t CR3; volatile uint32_t GTPR; }USART_RegDef_t; USART_RegDef_t *pUSART1= ((USART_RegDef_t*)USART1_BASEADDR); USART_RegDef_t *pUSART2= ((USART_RegDef_t*)USART2_BASEADDR); USART_RegDef_t *pUSART3= ((USART_RegDef_t*)USART3_BASEADDR); USART_RegDef_t *pUART4= ((USART_RegDef_t*)UART4_BASEADDR); USART_RegDef_t *pUART5= ((USART_RegDef_t*)UART5_BASEADDR); USART_RegDef_t *pUSART6= ((USART_RegDef_t*)USART6_BASEADDR); #define USART1 ((USART_RegDef_t*)USART1_BASEADDR) #define USART2 ((USART_RegDef_t*)USART2_BASEADDR) #define USART3 ((USART_RegDef_t*)USART3_BASEADDR) #define USART4 ((USART_RegDef_t*)UART4_BASEADDR) #define USART5 ((USART_RegDef_t*)UART5_BASEADDR) #define USART6 ((USART_RegDef_t*)USART6_BASEADDR) //DMA typedef struct { volatile uint32_t LISR; //0x000 volatile uint32_t HISR; //0x004 volatile uint32_t LIFCR; //0x008 volatile uint32_t HIFCR; //0x00C volatile uint32_t S0CR; //0x010 volatile uint32_t S0NDTR; //0x014 volatile uint32_t S0PAR; //0x018 volatile uint32_t S0M0AR; //0x01C volatile uint32_t S0M1AR; //0x020 volatile uint32_t S0FCR; //0x024 volatile uint32_t S1CR; //0x028 volatile uint32_t S1NDTR; //0x02C volatile uint32_t S1PAR; //0x030 volatile uint32_t S1M0AR; //0x034 volatile uint32_t S1M1AR; //0x038 volatile uint32_t S1FCR; //0x03C volatile uint32_t S2CR; //0x040 volatile uint32_t S2NDTR; //0x044 volatile uint32_t S2PAR; //0x048 volatile uint32_t S2M0AR; //0x04C volatile uint32_t S2M1AR; //0x050 volatile uint32_t S2FCR; //0x054 volatile uint32_t S3CR; //0x058 volatile uint32_t S3NDTR; //0x05C volatile uint32_t S3PAR; //0x060 volatile uint32_t S3M0AR; //0x064 volatile uint32_t S3M1AR; //0x068 volatile uint32_t S3FCR; //0x06C volatile uint32_t S4CR; //0x070 volatile uint32_t S4NDTR; //0x074 volatile uint32_t S4PAR; //0x078 volatile uint32_t S4M0AR; //0x07C volatile uint32_t S4M1AR; //0x080 volatile uint32_t S4FCR; //0x084 volatile uint32_t S5CR; //0x088 volatile uint32_t S5NDTR; //0x08C volatile uint32_t S5PAR; //0x090 volatile uint32_t S5M0AR; //0x094 volatile uint32_t S5M1AR; //0x098 volatile uint32_t S5FCR; //0x09C volatile uint32_t S6CR; //0x0A0 volatile uint32_t S6NDTR; //0x0A4 volatile uint32_t S6PAR; //0x0A8 volatile uint32_t S6M0AR; //0x0AC volatile uint32_t S6M1AR; //0x0B0 volatile uint32_t S6FCR; //0x0B4 volatile uint32_t S7CR; //0x0B8 volatile uint32_t S7NDTR; //0x0BC volatile uint32_t S7PAR; //0x0C0 volatile uint32_t S7M0AR; //0x0C4 volatile uint32_t S7M1AR; //0x0C8 volatile uint32_t S7FCR; //0x0CC }DMA_RegDef_t; DMA_RegDef_t *pDMA1= ((DMA_RegDef_t*)DMA1_BASEADDR); DMA_RegDef_t *pDMA2= ((DMA_RegDef_t*)DMA2_BASEADDR); #define DMA1 ((DMA_RegDef_t*)DMA1_BASEADDR) #define DMA2 ((DMA_RegDef_t*)DMA2_BASEADDR) #endif /* STM32F446_H_ */

So this header file contains all the definitions we need to create our main C file.

The contents of the main.c file is shown below.


#include <stdint.h> #include "stm32f446.h" void usart2_tx_init(void); static uint16_t compute_usart_bd(uint32_t PCLK, uint32_t Baudrate); void dma1_stream6_init(uint32_t src, uint32_t dst, uint32_t len); void DMA1_Stream6_IRQHandler(void); int main(void) { char message[31] = "STM32 Sample DMA Program- Tx\n\r"; //Enable clock access to GPIOA pRCC->AHB1ENR |= (1 << 0); //Set PA5 as an output pin pGPIOA->MODER |= (0b01 << 10); usart2_tx_init(); dma1_stream6_init((uint32_t) message, (uint32_t) &(pUSART2->DR), 31); while(1) { } } void usart2_tx_init(void) { //Turns on the clock for GPIO Port A pRCC->AHB1ENR |= (1 << 0); //Sets PA2 to alternate function mode pGPIOA->MODER |= (0b10 << 4); //Sets pin PA2 to USART2_TX pGPIOA->AFRL |= (0b0111 << 8); //Turn on USART2 clock pRCC->APB1ENR |= (1 << 17); pUSART2->BRR |= compute_usart_bd(APB1_CLK, USART_BAUDRATE); //Enables transmitter pUSART2->CR1 = (1 << 3); //Enables the USART pUSART2->CR1 |= (1 << 13); } static uint16_t compute_usart_bd(uint32_t PCLK, uint32_t Baudrate) { return ((PCLK + (Baudrate/2))/Baudrate); } void dma1_stream6_init(uint32_t src, uint32_t dst, uint32_t len) { //Enable clock access to DMA pRCC->AHB1ENR |= (1 << 21); //Disable DMA1 Stream 6 pDMA1->S6CR &= ~(1 << 0); //Wait until DA1 Stream 6 is disabled while((pDMA1->S6CR) & (1 << 0)); //Clear all interrupt flags for Stream 6 pDMA1->HIFCR |= (1 << 16); pDMA1->HIFCR |= (0b1111 << 18); //Set the destination buffer pDMA1->S6PAR = dst; //Set the source buffer pDMA1->S6M0AR= src; //Set the length. This register holds the length //of the transfer pDMA1->S6NDTR = len; //Select stream 6 channel 4 pDMA1->S6CR= (0b100 << 25); //Enable memory increment pDMA1->S6CR |= (1 << 10); //Set the transfer direction //Memory to peripheral transfer pDMA1->S6CR |= (1 << 6); //Enable DMA transfer complete interrupt pDMA1->S6CR |= (1 << 4); //Enable direct mode and disable FIFO mode pDMA1->S6FCR = 0; //Enable DMA Stream 6 pDMA1->S6CR |= (1 << 0); //Enable UART2 transmitter DMA pUSART2->CR3 |= (1 << 7); //DMA interrupt enable in NVIC *pNVIC_ISER0 |= (1 << 17); } void DMA1_Stream6_IRQHandler(void) { if((pDMA1->HISR) & (1 << 21)) { pDMA1->HIFCR |= (1 << 21); pGPIOA->ODR |= (1 << 5); } }

The first thing we must do is include the stdint.h header file and our stm32f446xx.h header file in our main.c file.

Next we have a few function prototypes listed so that the compiler knows all of the functions in our program, the arguments they take in, the return value of the function, etc.

We then have our main() function.

Before we get to this function, let us first go into the others.

The usart2_tx_init() function sets pin PA2 to USART2_TX, turns on the USART2 clock, sets the baud rate for UART communication, enables the transmitter, and enables the USART.

The compute_usart_bd() function calculates the baud rate for UART communication.

Next, we have our dma1_stream6_init() function.

This function takes in 3 parameters: src, dst, and len.

The source is the origin of the data.

The dst is the destination of the data.

len is how many bits of data you are transmitting.

The first thing we do is enable clock access to DMA. This is done in the AHB1ENR register by setting bit 21 to HIGH.

The first thing we need to do is disable DMA1 Stream 6. According to the datasheet, before setting EN bit to 1 to start a new transfer, the event flags corresponding to the stream in DMA_LISR or DMA_HISR must be cleared.

We disable DMA1 Stream 6 by writing a 0 to bit 0 of the SxCR register, or the DMA stream x configuration register (DMA_SxCR).

This register is shown below.

So this is a register we will be using frequently throughout the course of this program. It has many bits we need to configure in order to make this program work.

The first thing we need to do is clear bit 0, the EN bit (Stream enable). We do this through the following line, pDMA1->S6CR &= ~(1 << 0);

Just to make sure that the DMA1 Steam 6 has been disabled, we have the following while loop that waits until bit 0 is 0, while((pDMA1->S6CR) & (1 << 0));

As long as bit 0 is 1, the program will be stuck in that loop.

Next, we need to clear all interrupt flags for Stream 6.

We do this in the DMA high interrupt flag clear register (DMA_HIFCR) shown below.

All of the bits that end in 6 belong to steam 6 and, thus, need to be cleared.

In this case, this would be bits 16, 18, 19, 20, and 21. So we do this in code. According to the datasheets, bits are cleared in this register by setting the bit HIGH.

Next, we need to set the destination buffer.

The destination buffer is the destination for where we want the data transferred from DMA to end up. In this case with this program, it is at the address of USART2.

We store this in the DMA stream x peripheral address register (DMA_SxPAR) shown below.

This register holds the address of the destination for where the data is going to.

Next, we set the source buffer.

We store the source of the data in the DMA stream x memory 0 address register (DMA_SxM0AR) shown below.

Next we set the length of the data being transferred in regard to the number of bits we are sending.

We set the length by writing this number to the DMA stream x number of data register (DMA_SxNDTR) shown below.

Next we must select channel 4 as our desired configuration.

We do this in the configuration register, as we previously showed.

Bits 27:25 are the CHSEL, or channel selection bits. We want to select channel 4, so we write 100 to these bits.

Next, we must adjust the memory increment mode, bit 10, of the same configuration register. We want the memory address pointer to increment after each data transfer, so we set this bit HIGH. According to the datasheet, increment is done according to MSIZE. By default, MSIZE sends one byte (or 8 bits) at a time. You can adjust MSIZE as needed for your program to be a half-word (16 bits) or a word (32 bits). In this case, we are sending the default 8 bits.

Next we set the data transfer direction, bits 7:6 of the configuration register. Because we are sending data from DMA to a peripheral device, we set this bit to memory-to-peripheral. We write 01 to these 2 bits.

Next, we want an interrupt to be generated when the DMA transfer is complete. This means that we set bit 4, the TCIE (transfer complete interrupt enable) bit, to HIGH. This will trigger an interrupt once all of the data from DMA has been transferred to the peripheral device.

Next we want to disable FIFO mode and enable direct mode. We don't necessarily want the data we entered first to be the last out. Instead we just want the data we created to be transferred directly as is. So we are to able to do this by simply clearing out the entire register.

By clearing this register, we disable FIFO mode and enable direct mode.

Next, we enable DMA Stream 6 by setting bit 0, the EN (Stream Enable) bit, to HIGH in the configuration register.

Next, we need to enable USART2 transmitter for DMA.

This is done in the USART Control Register 3 shown below.

Looking at bit 7, the DMAT bit, this is how we can enable the DMA transmitter. By setting this bit to HIGH, DMA mode is enabled for transmission.

Lastly, we must enable the interrupt on the NVIC on the processor side.

Looking the value of the IRQ number up on the vector table, we see that the DMA has an IRQ number of 17.

This means that we must set the 17th bit to HIGH in the ISER0 register, which is what we do in the following line, *pNVIC_ISER0 |= (1 << 17);

Next, we go to our interrupt service routine for the DMA.

Remember that we trigger an interrupt after the complete DMA transfer is complete.

Once this transfer is completed, the interrupt service routine will be executed.

We need to check the DMA high interrupt status register (DMA_HISR) to check if the transfer is complete. This is done by checking if bit 21 is HIGH. Bit 21 is TCIF6, which the Transfer Complete Interrupt Flag for Stream 6.

If this bit is HIGH, we clear it in the DMA high interrupt flag clear register (DMA_HIFCR) by writing HIGH to bit 21.

We then turn on an LED just to show that this interrupt is executed in addition to transferring the data from DMA to the peripheral device.

Now we go back to our main() function.

Within this main() function, we create data that we are going to transfer.

This data is the variable, message, which is an array of type char, which has a length of 31.

Because we want to also turn on an LED in addition to sending the data when an interrupt occurs, we enable clock access to GPIOA and we set pin PA5 as an output pin.

We then initialize the UART communication through the line, usart2_tx_init();

We then use the dma1_stream6_int() function to send data from DMA to a peripheral device via UART communication.

We must specify 3 parameters with this function, including the data we are sending (in this case, message), the address of the destination (in this case, &pUSART2->DR), and the length of the data.

We then can execute our code and open the RealTerm software. Remember in the RealTerm software to specify a baud rate of 115200 and the correct USB port where your STM32 board is connected to.

Afterwards, you may have to open and close the port, and then you should see the message come through on the monitor.

And this is what is needed to transmit data from direct memory access to a peripheral device.

DMA comes especially in hand when you are transferring large amounts of data, so that the CPU processing isn't tied down.

So this is how to transmit data from direct memory access to a peripheral device with an STM32F446 microcontroller board.

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