How to Create a SysTick Timer Interrupt Driver with an STM32F446 Microcontroller Board in C

In this article, we explain how to create a SysTick timer interrupt driver with an STM32F446 microcontroller board in C.

With a SysTick timer interrupt driver, we can have a timer running that can execute some specific task at some specific interval we determine.

In our program, we will have a SysTick timer interrupt driver which will have a 1-second delay and toggle an LED every second.

Previously, we created a program on, How to Create a Delay using the SysTick Timer with an STM32F446 Board in C. If you need to, please familiarize yourself with how to create a delay with a SysTick timer first before using interrupts, because we will not go over that code as extensively; we will simply be going over how to turn that code into it being done with an interrupt driver.

So we take this program and modify it a bit by enabling the UIE interrupt bit in the TIMx DMA/Interrupt enable register and then enabling the interrupt for UART on the processor side, meaning for the Cortex-M4 processor.

We do both of these tasks within the the code to initialize the timer 2.

The next thing we need is an interrupt service routine for the timer. This is the function our code will execute when an interrupt does occur. In this case, we will toggle an LED on and off at a 1-second interval. It's simply to demonstrate how we can run code through an interrupt service routine.

We need 3 major code files in order for this code to work.

We need our header files, which contains many macros and structures that describe the various registers and needed values.

We then need our main C file, which contains the code of the timer interrupt driver.

Below is the systick.h header file, which contains many macros and registers for the SysTick timer.


/* * systick.h * * Created on: May 10, 2022 * Author: dlhyl */ #ifndef INC_SYSTICK_H_ #define INC_SYSTICK_H_ #define SYSTICK_BASEADDR 0xE000E010 typedef struct { volatile uint32_t CSR; //SysTick Control and Status Register volatile uint32_t RVR; //SysTick Reload Value Register volatile uint32_t CVR; //SysTick Current Value Register volatile uint32_t CALIB; //SysTick Calibration Value Register }SysTick_RegDef_t; SysTick_RegDef_t *pSysTick= ((SysTick_RegDef_t*)SYSTICK_BASEADDR); #define SYSTICK ((SysTick_RegDef_t*)SYSTICK_BASEADDR) #endif /* INC_SYSTICK_H_ */

Below is the header file which in this case is named, stm32f407xx.h


/* * stm32f446.h * * Created on: May 6, 2022 * Author: dlhyl */ #ifndef STM32F446_H_ #define STM32F446_H_ #include <stdint.h> #define __vo volatile #define IRQ_NO_EXTI0 6 #define IRQ_NO_EXTI1 7 #define IRQ_NO_EXTI2 8 #define IRQ_NO_EXTI3 9 #define IRQ_NO_EXTI4 10 #define IRQ_NO_EXTI9_5 23 #define IRQ_NO_EXTI15_10 40 //Processor specific details #define NVIC_ISER0 0xE000E100U #define NVIC_ISER1 0xE000E104U #define NVIC_ISER2 0xE000E108U #define NVIC_ISER3 0xE000E10CU volatile uint32_t* pNVIC_ISER0= ((volatile uint32_t*)NVIC_ISER0); volatile uint32_t* pNVIC_ISER1= ((volatile uint32_t*)NVIC_ISER1); volatile uint32_t* pNVIC_ISER2= ((volatile uint32_t*)NVIC_ISER2); volatile uint32_t* pNVIC_ISER3= ((volatile uint32_t*)NVIC_ISER3); #define NVIC_ICER0 0xE000E180U #define NVIC_ICER1 0xE000E184U #define NVIC_ICER2 0xE000E188U #define NVIC_ICER3 0xE000E18CU volatile uint32_t* pNVIC_ICERO= ((volatile uint32_t*)NVIC_ICER0); volatile uint32_t* pNVIC_ICER1= ((volatile uint32_t*)NVIC_ICER1); volatile uint32_t* pNVIC_ICER2= ((volatile uint32_t*)NVIC_ICER2); volatile uint32_t* pNVIC_ICER3= ((volatile uint32_t*)NVIC_ICER3); #define NVIC_PR_BASEADDR 0xE000E400U volatile uint32_t* pNVIC_PR_BASEADDR= ((volatile uint32_t*)NVIC_PR_BASEADDR); #define SYS_FREQ 16000000U #define APB1_CLK SYS_FREQ #define USART_BAUDRATE 115200 #define FLASH_BASEADDR 0x08000000U #define SRAM1_BASEADDR 0x20000000U #define SRAM2_BASEADDR 0x20001C00U #define ROM_BASEADDR 0x1FFF0000U #define SRAM SRAM1_BASEADDR #define PERIPH_BASEADDR 0x40000000U #define APB1PERIPH_BASEADDR PERIPH_BASEADDR #define APB2PERIPH_BASEADDR 0x40010000U #define AHB1PERIPH_BASEADDR 0x40020000U #define AHB2PERIPH_BASEADDR 0x50000000U //#define SYSCFG_BASEADDR 0x40013800U //#define EXTI_BASEADDR 0x40013C00U #define GPIOA_BASEADDR (AHB1PERIPH_BASEADDR + 0x0000) #define GPIOB_BASEADDR (AHB1PERIPH_BASEADDR + 0x0400) #define GPIOC_BASEADDR (AHB1PERIPH_BASEADDR + 0x0800) #define GPIOD_BASEADDR (AHB1PERIPH_BASEADDR + 0x0C00) #define GPIOE_BASEADDR (AHB1PERIPH_BASEADDR + 0x1000) #define GPIOF_BASEADDR (AHB1PERIPH_BASEADDR + 0x1400) #define GPIOG_BASEADDR (AHB1PERIPH_BASEADDR + 0x1800) #define GPIOH_BASEADDR (AHB1PERIPH_BASEADDR + 0x1C00) #define GPIOI_BASEADDR (AHB1PERIPH_BASEADDR + 0x2000) #define RCC_BASEADDR (AHB1PERIPH_BASEADDR + 0x3800) #define I2C1_BASEADDR (APB1PERIPH_BASEADDR + 0x5400) #define I2C2_BASEADDR (APB1PERIPH_BASEADDR + 0x5800) #define I2C3_BASEADDR (APB1PERIPH_BASEADDR + 0x5C00) #define SPI2_BASEADDR (APB1PERIPH_BASEADDR + 0x3800) #define SPI3_BASEADDR (APB1PERIPH_BASEADDR + 0x3C00) #define USART2_BASEADDR (APB1PERIPH_BASEADDR + 0x4400) #define USART3_BASEADDR (APB1PERIPH_BASEADDR + 0x4800) #define UART4_BASEADDR (APB1PERIPH_BASEADDR + 0x4C00) #define UART5_BASEADDR (APB1PERIPH_BASEADDR + 0x5000) #define EXTI_BASEADDR (APB2PERIPH_BASEADDR + 0x3C00) #define SPI1_BASEADDR (APB2PERIPH_BASEADDR + 0x3000) #define SPI4_BASEADDR (APB2PERIPH_BASEADDR + 0x3400) #define SYSCFG_BASEADDR (APB2PERIPH_BASEADDR + 0x3800) #define USART1_BASEADDR (APB2PERIPH_BASEADDR + 0x1000) #define USART6_BASEADDR (APB2PERIPH_BASEADDR + 0x1400) #define SPI5_BASEADDR (APB2PERIPH_BASEADDR + 0x5000) #define SPI6_BASEADDR (APB2PERIPH_BASEADDR + 0x5400) typedef struct { volatile uint32_t MODER; volatile uint32_t OTYPER; volatile uint32_t OSPEEDR; volatile uint32_t PUPDR; volatile uint32_t IDR; volatile uint32_t ODR; volatile uint32_t BSRR; volatile uint32_t LCKR; volatile uint32_t AFRL; volatile uint32_t AFRH; }GPIO_RegDef_t; #define GPIOA ((GPIO_RegDef_t*)GPIOA_BASEADDR) #define GPIOB ((GPIO_RegDef_t*)GPIOB_BASEADDR) #define GPIOC ((GPIO_RegDef_t*)GPIOC_BASEADDR) #define GPIOD ((GPIO_RegDef_t*)GPIOD_BASEADDR) #define GPIOE ((GPIO_RegDef_t*)GPIOE_BASEADDR) #define GPIOF ((GPIO_RegDef_t*)GPIOF_BASEADDR) #define GPIOG ((GPIO_RegDef_t*)GPIOG_BASEADDR) #define GPIOH ((GPIO_RegDef_t*)GPIOH_BASEADDR) #define GPIOI ((GPIO_RegDef_t*)GPIOI_BASEADDR) #define RCC ((RCC_RegDef_t*)RCC_BASEADDR) GPIO_RegDef_t *pGPIOA= GPIOA; GPIO_RegDef_t *pGPIOB= GPIOB; GPIO_RegDef_t *pGPIOC= GPIOC; GPIO_RegDef_t *pGPIOD= GPIOD; GPIO_RegDef_t *pGPIOE= GPIOE; GPIO_RegDef_t *pGPIOF= GPIOF; GPIO_RegDef_t *pGPIOG= GPIOG; GPIO_RegDef_t *pGPIOH= GPIOH; GPIO_RegDef_t *pGPIOI= GPIOI; typedef struct { volatile uint32_t CR; volatile uint32_t PLLCFGR; volatile uint32_t CFGR; volatile uint32_t CIR; volatile uint32_t AHB1RSTR; volatile uint32_t AHB2RSTR; volatile uint32_t AHB3RSTR; uint32_t RESERVED0; volatile uint32_t APB1RSTR; volatile uint32_t APB2RSTR; uint32_t RESERVED1[2]; volatile uint32_t AHB1ENR; volatile uint32_t AHB2ENR; volatile uint32_t AHB3ENR; uint32_t RESERVED2; volatile uint32_t APB1ENR; volatile uint32_t APB2ENR; uint32_t RESERVED3[2]; volatile uint32_t AHB1LPENR; volatile uint32_t AHB2LPENR; volatile uint32_t AHB3LPENR; uint32_t RESERVED4; volatile uint32_t APB1LPENR; volatile uint32_t APB2LPENR; uint32_t RESERVED5[2]; volatile uint32_t BDCR; volatile uint32_t CSR; uint32_t RESERVED6[2]; volatile uint32_t SSCGR; volatile uint32_t PLLI2SCFGR; volatile uint32_t PLLSAICFGR; volatile uint32_t DCKCFGR; volatile uint32_t CKGATENR; volatile uint32_t DCKCFGR2; }RCC_RegDef_t; RCC_RegDef_t *pRCC= RCC; typedef struct { volatile uint32_t MEMRMP; volatile uint32_t PMC; volatile uint32_t EXTICR1; volatile uint32_t EXTICR2; volatile uint32_t EXTICR3; volatile uint32_t EXTICR4; uint32_t RESERVED1[2]; volatile uint32_t CMPCR; }SYSCFG_RegDef_t; SYSCFG_RegDef_t *pSYSCFG= ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR); #define SYSCFG ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR) typedef struct { volatile uint32_t IMR; volatile uint32_t EMR; volatile uint32_t RTSR; volatile uint32_t FTSR; volatile uint32_t SWIER; volatile uint32_t PR; }EXTI_RegDef_t; EXTI_RegDef_t *pEXTI= ((EXTI_RegDef_t*)EXTI_BASEADDR); #define EXTI ((EXTI_RegDef_t*)EXTI_BASEADDR) typedef struct { volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t SR; volatile uint32_t DR; volatile uint32_t CRCPR; volatile uint32_t RXCRCR; volatile uint32_t TXCRCR; volatile uint32_t I2SCFGR; volatile uint32_t I2SPR; }SPI_RegDef_t; SPI_RegDef_t *pSPI1= ((SPI_RegDef_t*)SPI1_BASEADDR); SPI_RegDef_t *pSPI2= ((SPI_RegDef_t*)SPI2_BASEADDR); SPI_RegDef_t *pSPI3= ((SPI_RegDef_t*)SPI3_BASEADDR); SPI_RegDef_t *pSPI4= ((SPI_RegDef_t*)SPI4_BASEADDR); SPI_RegDef_t *pSPI5= ((SPI_RegDef_t*)SPI5_BASEADDR); SPI_RegDef_t *pSPI6= ((SPI_RegDef_t*)SPI6_BASEADDR); #define SPI1 ((SPI_RegDef_t*)SPI1_BASEADDR) #define SPI2 ((SPI_RegDef_t*)SPI2_BASEADDR) #define SPI3 ((SPI_RegDef_t*)SPI3_BASEADDR) #define SPI4 ((SPI_RegDef_t*)SPI4_BASEADDR) #define SPI5 ((SPI_RegDef_t*)SPI5_BASEADDR) #define SPI6 ((SPI_RegDef_t*)SPI6_BASEADDR) typedef struct { volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t OAR1; volatile uint32_t OAR2; volatile uint32_t DR; volatile uint32_t SR1; volatile uint32_t SR2; volatile uint32_t CCR; volatile uint32_t TRISE; volatile uint32_t FLTR; }I2C_RegDef_t; I2C_RegDef_t *pI2C1= ((I2C_RegDef_t*)I2C1_BASEADDR); I2C_RegDef_t *pI2C2= ((I2C_RegDef_t*)I2C2_BASEADDR); I2C_RegDef_t *pI2C3= ((I2C_RegDef_t*)I2C3_BASEADDR); #define I2C1 ((I2C_RegDef_t*)I2C1_BASEADDR) #define I2C2 ((I2C_RegDef_t*)I2C2_BASEADDR) #define I2C3 ((I2C_RegDef_t*)I2C3_BASEADDR) typedef struct { volatile uint32_t SR; volatile uint32_t DR; volatile uint32_t BRR; volatile uint32_t CR1; volatile uint32_t CR2; volatile uint32_t CR3; volatile uint32_t GTPR; }USART_RegDef_t; USART_RegDef_t *pUSART1= ((USART_RegDef_t*)USART1_BASEADDR); USART_RegDef_t *pUSART2= ((USART_RegDef_t*)USART2_BASEADDR); USART_RegDef_t *pUSART3= ((USART_RegDef_t*)USART3_BASEADDR); USART_RegDef_t *pUART4= ((USART_RegDef_t*)UART4_BASEADDR); USART_RegDef_t *pUART5= ((USART_RegDef_t*)UART5_BASEADDR); USART_RegDef_t *pUSART6= ((USART_RegDef_t*)USART6_BASEADDR); #define USART1 ((USART_RegDef_t*)USART1_BASEADDR) #define USART2 ((USART_RegDef_t*)USART2_BASEADDR) #define USART3 ((USART_RegDef_t*)USART3_BASEADDR) #define USART4 ((USART_RegDef_t*)UART4_BASEADDR) #define USART5 ((USART_RegDef_t*)UART5_BASEADDR) #define USART6 ((USART_RegDef_t*)USART6_BASEADDR) #endif /* STM32F446_H_ */

So this header file contains all the definitions we need to create our main C file.

The contents of the main.c file is shown below.


#include <stdint.h> #include "stm32f446.h" #include "systick.h" void systick_1hz_interrupt(void); void SysTick_Handler(void); int main(void) { //Turn on peripheral clock for GPIO Port A pRCC->AHB1ENR |= (1 << 0); //Set PA5 as the output pin pGPIOA->MODER |= (0b01 << 10); systick_1hz_interrupt(); while(1) { } } void systick_1hz_interrupt(void) { //Sets the reload value pSysTick->RVR = 16000000; //Clears the SysTick current value register pSysTick->CVR= 0; //Enable SysTick in the control register and select internal system clock source pSysTick->CSR= (1 << 0) | (1 << 2); //Enable systick interrupt pSysTick->CSR |= (1 << 1); } void SysTick_Handler(void) { pGPIOA->ODR ^= (1 << 5); }

We will now go over the code.

So we place the prototypes of our functions into our code.

We then have our main() function.

We turn on the peripheral clock for GPIO Port A. We then set pin PA5 as output, which on the STM32F446 board is connected to an onboard green LED.

We then initialize the SysTick timer with the systick_1hz_interrupt() function.

Our infinite while loop is empty.

We then have our systick_1hz_interrupt() function.

In this function, we set the reload value to 16000000, which makes the timer have a 1-second delay.

We clear the SysTick current value register, so that any residual number in it is cleared.

We then enable the SysTick timer in the control register and select the internal system clock source.

Lastly, we enable the systick interrupt in the control register by setting the TICKINT bit, bit 1, to HIGH, which enables the SysTick exception request.

The SysTick control and status register (SYS_CSR) is shown below.

We then go to our SysTick_Handler() interrupt service routine function. In this function, we simply toggle the LED at pin PA5.

The SysTick timer interrupt is one of the easiest to implement, as no IRQ number is needed.

The program will now toggle an LED on and off every 1 second.

And this is how we can code a SysTick timer interrupt driver with an STM32F446 board in C.

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